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| author | Richard Henderson <rth@twiddle.net> | 2010-02-16 14:10:13 -0800 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2010-02-20 08:33:31 +0000 |
| commit | 241cbed4a992e31e718f56f831d7dd30fec5b55b (patch) | |
| tree | 69a781fe03b60a31000e8d7c72082f6ce0ea4b11 /tcg/tcg-op.h | |
| parent | be6551b1e757fab6b3e43aa8833f655a7745204a (diff) | |
| download | qemu-241cbed4a992e31e718f56f831d7dd30fec5b55b.tar.gz | |
tcg: Optional target implementation of ANDC.
Previously ANDC was always implemented by tcg-op.h with
an explicit NOT opcode. Allow a target implementation.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'tcg/tcg-op.h')
| -rw-r--r-- | tcg/tcg-op.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 13eaa5a9e8..447878db01 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -1650,20 +1650,31 @@ static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 hi static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { +#ifdef TCG_TARGET_HAS_andc_i32 + tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2); +#else TCGv_i32 t0; t0 = tcg_temp_new_i32(); tcg_gen_not_i32(t0, arg2); tcg_gen_and_i32(ret, arg1, t0); tcg_temp_free_i32(t0); +#endif } static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { +#ifdef TCG_TARGET_HAS_andc_i64 + tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2); +#elif defined(TCG_TARGET_HAS_andc_i32) && TCG_TARGET_REG_BITS == 32 + tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); + tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); +#else TCGv_i64 t0; t0 = tcg_temp_new_i64(); tcg_gen_not_i64(t0, arg2); tcg_gen_and_i64(ret, arg1, t0); tcg_temp_free_i64(t0); +#endif } static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |