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| author | Richard Henderson <rth@twiddle.net> | 2013-02-19 23:51:49 -0800 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2013-02-23 17:25:28 +0000 |
| commit | e6a72734549bd05d06d19957518811c24a6cbee4 (patch) | |
| tree | 4d6178a6356a6e918d240dcbb3fc9a0394b72dcc /tcg/tcg-opc.h | |
| parent | f708e736d0dafc05f8b7e9e73d6440c930b94686 (diff) | |
| download | qemu-e6a72734549bd05d06d19957518811c24a6cbee4.tar.gz | |
tcg: Make 32-bit multiword operations optional for 64-bit hosts
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'tcg/tcg-opc.h')
| -rw-r--r-- | tcg/tcg-opc.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 9651063414..1d9a9a22ab 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -83,10 +83,10 @@ DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32)) DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END) -DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_REG_BITS == 32)) -DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_REG_BITS == 32)) +DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2_i32)) +DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_sub2_i32)) +DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_mulu2_i32)) DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | IMPL(TCG_TARGET_REG_BITS == 32)) -DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_REG_BITS == 32)) DEF(setcond2_i32, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS == 32)) DEF(ext8s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32)) |