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| author | Stefan Weil <sw@weilnetz.de> | 2012-09-18 22:43:38 +0200 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2012-09-27 21:28:25 +0200 |
| commit | 6673f47da21718d07346b0f3725f0dbf0d6d8e45 (patch) | |
| tree | 0b99abc812e847593fc8c485aacc0eb270a164bc /tcg/tci | |
| parent | ac05f3492421caeb05809ffa02c6198ede179e43 (diff) | |
| download | qemu-6673f47da21718d07346b0f3725f0dbf0d6d8e45.tar.gz | |
tci: Fix for AREG0 free mode
Support for helper functions with 5 arguments was missing
in the code generator and in the interpreter.
There is no need to pass the constant TCG_AREG0 from the
code generator to the interpreter. Remove that code for
the INDEX_op_qemu_st* opcodes.
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'tcg/tci')
| -rw-r--r-- | tcg/tci/tcg-target.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/tcg/tci/tcg-target.c b/tcg/tci/tcg-target.c index 3f4a24bb8b..d272a906e8 100644 --- a/tcg/tci/tcg-target.c +++ b/tcg/tci/tcg-target.c @@ -300,7 +300,7 @@ static const int tcg_target_reg_alloc_order[] = { #endif }; -#if MAX_OPC_PARAM_IARGS != 4 +#if MAX_OPC_PARAM_IARGS != 5 # error Fix needed, number of supported input arguments changed! #endif @@ -309,16 +309,18 @@ static const int tcg_target_call_iarg_regs[] = { TCG_REG_R1, TCG_REG_R2, TCG_REG_R3, -#if TCG_TARGET_REG_BITS == 32 - /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */ #if 0 /* used for TCG_REG_CALL_STACK */ TCG_REG_R4, #endif TCG_REG_R5, +#if TCG_TARGET_REG_BITS == 32 + /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */ TCG_REG_R6, TCG_REG_R7, #if TCG_TARGET_NB_REGS >= 16 TCG_REG_R8, + TCG_REG_R9, + TCG_REG_R10, #else # error Too few input registers available #endif @@ -798,7 +800,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_qemu_st8: case INDEX_op_qemu_st16: case INDEX_op_qemu_st32: - tcg_out_r(s, TCG_AREG0); tcg_out_r(s, *args++); tcg_out_r(s, *args++); #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS @@ -809,7 +810,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, #endif break; case INDEX_op_qemu_st64: - tcg_out_r(s, TCG_AREG0); tcg_out_r(s, *args++); #if TCG_TARGET_REG_BITS == 32 tcg_out_r(s, *args++); |