diff options
| author | Aurelien Jarno <aurelien@aurel32.net> | 2013-09-03 08:27:38 +0200 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2014-02-17 10:12:28 -0600 |
| commit | f096dc96188378bc2bcd80683490ca386b0c1683 (patch) | |
| tree | d17d247a76ec1d516625016848607b2886a914de /tcg | |
| parent | 3031244b01492528fd7b5e46b23eeb2124dc780a (diff) | |
| download | qemu-f096dc96188378bc2bcd80683490ca386b0c1683.tar.gz | |
tcg/optimize: improve known-zero bits for 32-bit ops
The shl_i32 op might set some bits of the unused 32 high bits of the
mask. Fix that by clearing the unused 32 high bits for all 32-bit ops
except load/store which operate on tl values.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg')
| -rw-r--r-- | tcg/optimize.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/tcg/optimize.c b/tcg/optimize.c index 7838be2c50..1cf017aab8 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -783,6 +783,12 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr, break; } + /* 32-bit ops (non 64-bit ops and non load/store ops) generate 32-bit + results */ + if (!(tcg_op_defs[op].flags & (TCG_OPF_CALL_CLOBBER | TCG_OPF_64BIT))) { + mask &= 0xffffffffu; + } + if (mask == 0) { assert(def->nb_oargs == 1); s->gen_opc_buf[op_index] = op_to_movi(op); |