diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2014-02-25 11:54:40 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-02-25 11:54:40 +0000 |
| commit | 05fd3bf2a1c9fc26414d3cf608732c40d0d9eb23 (patch) | |
| tree | 89e1d86090aca653216eef7ca1503797fb0a0931 /tests/tcg/xtensa/Makefile | |
| parent | e7a1d6c52a3ac6e76e5653c830b2545e0a4043d3 (diff) | |
| parent | 604e1f9cd0602e92ba49a27dd3a46db3d29f882e (diff) | |
| download | qemu-05fd3bf2a1c9fc26414d3cf608732c40d0d9eb23.tar.gz | |
Merge remote-tracking branch 'remotes/xtensa/tags/20140224-xtensa' into staging
Xtensa fixes and improvements queue 2014-02-24:
- add support for ML605 and KC705 FPGA boards;
- flush opencores_eth queue when new RX descriptor is available;
- add basic checks to cache opcodes;
- make core configuration available to tests;
- implement HW config ID special registers.
# gpg: Signature made Mon 24 Feb 2014 00:52:42 GMT using RSA key ID F83FA044
# gpg: Good signature from "Max Filippov <max.filippov@cogentembedded.com>"
# gpg: aka "Max Filippov <jcmvbkbc@gmail.com>"
* remotes/xtensa/tags/20140224-xtensa:
target-xtensa: provide HW confg ID registers
target-xtensa: refactor standard core configuration
target-xtensa: add basic tests for cache opcodes
target-xtensa: allow using core configuration in tests
target-xtensa: add overridable test_init macro
target-xtensa: add basic checks to icache opcodes
target-xtensa: add basic checks to dcache opcodes
target-xtensa: add RRRI4 opcode format fields
opencores_eth: flush queue whenever can_receive can go from false to true
hw/xtensa: add support for ML605 and KC705 FPGA board
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'tests/tcg/xtensa/Makefile')
| -rw-r--r-- | tests/tcg/xtensa/Makefile | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/tests/tcg/xtensa/Makefile b/tests/tcg/xtensa/Makefile index 1b519cae45..a70c92be7e 100644 --- a/tests/tcg/xtensa/Makefile +++ b/tests/tcg/xtensa/Makefile @@ -1,10 +1,11 @@ -include ../../../config-host.mak -CROSS=xtensa-dc232b-elf- +CORE=dc232b +CROSS=xtensa-$(CORE)-elf- ifndef XT SIM = ../../../xtensa-softmmu/qemu-system-xtensa -SIMFLAGS = -M sim -cpu dc232b -nographic -semihosting $(EXTFLAGS) -kernel +SIMFLAGS = -M sim -cpu $(CORE) -nographic -semihosting $(EXTFLAGS) -kernel SIMDEBUG = -s -S else SIM = xt-run @@ -17,6 +18,8 @@ AS = $(CROSS)gcc -x assembler-with-cpp LD = $(CROSS)ld XTENSA_SRC_PATH = $(SRC_PATH)/tests/tcg/xtensa +INCLUDE_DIRS = $(XTENSA_SRC_PATH) $(SRC_PATH)/target-xtensa/core-$(CORE) +XTENSA_INC = $(addprefix -I,$(INCLUDE_DIRS)) LDFLAGS = -T$(XTENSA_SRC_PATH)/linker.ld @@ -27,6 +30,7 @@ TESTCASES += test_bi.tst #TESTCASES += test_boolean.tst TESTCASES += test_break.tst TESTCASES += test_bz.tst +TESTCASES += test_cache.tst TESTCASES += test_clamps.tst TESTCASES += test_extui.tst TESTCASES += test_fail.tst @@ -56,10 +60,10 @@ TESTCASES += test_windowed.tst all: build %.o: $(XTENSA_SRC_PATH)/%.c - $(CC) -I$(XTENSA_SRC_PATH) $(CFLAGS) -c $< -o $@ + $(CC) $(XTENSA_INC) $(CFLAGS) -c $< -o $@ %.o: $(XTENSA_SRC_PATH)/%.S - $(AS) -Wa,-I,$(XTENSA_SRC_PATH) $(ASFLAGS) -c $< -o $@ + $(CC) $(XTENSA_INC) $(ASFLAGS) -c $< -o $@ %.tst: %.o $(XTENSA_SRC_PATH)/macros.inc $(CRT) Makefile $(LD) $(LDFLAGS) $(NOSTDFLAGS) $(CRT) $< -o $@ |