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authorbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2003-06-24 13:28:48 +0000
committerbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2003-06-24 13:28:48 +0000
commit7d83131cc5ea95d7bb98658ac958a901ba4269de (patch)
tree01a9533b51a00d71b03206f5b61dfc8683153053 /translate-arm.c
parent66e85a21c7f65540ac1976ed29ed9973089fe1f1 (diff)
downloadqemu-7d83131cc5ea95d7bb98658ac958a901ba4269de.tar.gz
use inline function
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@263 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'translate-arm.c')
-rw-r--r--translate-arm.c12
1 files changed, 11 insertions, 1 deletions
diff --git a/translate-arm.c b/translate-arm.c
index 9b85b68513..2413f02a55 100644
--- a/translate-arm.c
+++ b/translate-arm.c
@@ -655,7 +655,7 @@ static void disas_arm_insn(DisasContext *s)
/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
basic block 'tb'. If search_pc is TRUE, also generate PC
information for each intermediate instruction. */
-int gen_intermediate_code(TranslationBlock *tb, int search_pc)
+static inline int gen_intermediate_code_internal(TranslationBlock *tb, int search_pc)
{
DisasContext dc1, *dc = &dc1;
uint16_t *gen_opc_end;
@@ -717,6 +717,16 @@ int gen_intermediate_code(TranslationBlock *tb, int search_pc)
return 0;
}
+int gen_intermediate_code(TranslationBlock *tb)
+{
+ return gen_intermediate_code_internal(tb, 0);
+}
+
+int gen_intermediate_code_pc(TranslationBlock *tb)
+{
+ return gen_intermediate_code_internal(tb, 1);
+}
+
CPUARMState *cpu_arm_init(void)
{
CPUARMState *env;