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| author | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2003-07-26 12:06:08 +0000 |
|---|---|---|
| committer | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2003-07-26 12:06:08 +0000 |
| commit | 4c3a88a284b288e0ed3c097de7fc07111d848003 (patch) | |
| tree | 8f4a8190c97d326f26b4e7d603ac8f98c50e8706 /translate-arm.c | |
| parent | d6b4936796b37f629879de69d847c5cdc4892157 (diff) | |
| download | qemu-4c3a88a284b288e0ed3c097de7fc07111d848003.tar.gz | |
gdb stub breakpoints support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@332 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'translate-arm.c')
| -rw-r--r-- | translate-arm.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/translate-arm.c b/translate-arm.c index c9759f81b7..bc8be855fb 100644 --- a/translate-arm.c +++ b/translate-arm.c @@ -786,7 +786,9 @@ static void disas_arm_insn(DisasContext *s) /* generate intermediate code in gen_opc_buf and gen_opparam_buf for basic block 'tb'. If search_pc is TRUE, also generate PC information for each intermediate instruction. */ -static inline int gen_intermediate_code_internal(TranslationBlock *tb, int search_pc) +static inline int gen_intermediate_code_internal(CPUState *env, + TranslationBlock *tb, + int search_pc) { DisasContext dc1, *dc = &dc1; uint16_t *gen_opc_end; @@ -853,14 +855,14 @@ static inline int gen_intermediate_code_internal(TranslationBlock *tb, int searc return 0; } -int gen_intermediate_code(TranslationBlock *tb) +int gen_intermediate_code(CPUState *env, TranslationBlock *tb) { - return gen_intermediate_code_internal(tb, 0); + return gen_intermediate_code_internal(env, tb, 0); } -int gen_intermediate_code_pc(TranslationBlock *tb) +int gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb) { - return gen_intermediate_code_internal(tb, 1); + return gen_intermediate_code_internal(env, tb, 1); } CPUARMState *cpu_arm_init(void) |