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-rw-r--r--MAINTAINERS1
-rwxr-xr-xconfigure3
-rw-r--r--hw/char/cadence_uart.c3
-rw-r--r--hw/misc/macio/cuda.c4
-rw-r--r--pc-bios/openbios-ppcbin750684 -> 750684 bytes
-rw-r--r--pc-bios/openbios-sparc32bin381584 -> 381584 bytes
-rw-r--r--pc-bios/openbios-sparc64bin1592280 -> 1592280 bytes
-rw-r--r--qemu-seccomp.c9
m---------roms/openbios0
-rw-r--r--target-i386/cpu.c16
-rw-r--r--target-ppc/cpu.h10
-rw-r--r--target-ppc/machine.c2
-rw-r--r--target-ppc/mem_helper.c5
-rw-r--r--target-ppc/translate.c6
14 files changed, 38 insertions, 21 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 1c30dfa993..28e2b17049 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1050,7 +1050,6 @@ M: Andreas Färber <afaerber@suse.de>
S: Supported
F: qom/cpu.c
F: include/qom/cpu.h
-F: target-i386/cpu.c
ICC Bus
M: Igor Mammedov <imammedo@redhat.com>
diff --git a/configure b/configure
index 5db29f0245..f1c307bfc6 100755
--- a/configure
+++ b/configure
@@ -1872,6 +1872,9 @@ if test "$seccomp" != "no" ; then
i386|x86_64)
libseccomp_minver="2.1.0"
;;
+ mips)
+ libseccomp_minver="2.2.0"
+ ;;
arm|aarch64)
libseccomp_minver="2.2.3"
;;
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index 486591bf07..797787823e 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -375,6 +375,9 @@ static void uart_write(void *opaque, hwaddr offset,
DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value);
offset >>= 2;
+ if (offset >= CADENCE_UART_R_MAX) {
+ return;
+ }
switch (offset) {
case R_IER: /* ier (wts imr) */
s->r[R_IMR] |= value;
diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c
index c7472aaa9d..f15f301100 100644
--- a/hw/misc/macio/cuda.c
+++ b/hw/misc/macio/cuda.c
@@ -685,8 +685,8 @@ static bool cuda_cmd_set_time(CUDAState *s,
return false;
}
- ti = (((uint32_t)in_data[1]) << 24) + (((uint32_t)in_data[2]) << 16)
- + (((uint32_t)in_data[3]) << 8) + in_data[4];
+ ti = (((uint32_t)in_data[0]) << 24) + (((uint32_t)in_data[1]) << 16)
+ + (((uint32_t)in_data[2]) << 8) + in_data[3];
s->tick_offset = ti - (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)
/ NANOSECONDS_PER_SECOND);
return true;
diff --git a/pc-bios/openbios-ppc b/pc-bios/openbios-ppc
index 4a883843e5..ff980adb12 100644
--- a/pc-bios/openbios-ppc
+++ b/pc-bios/openbios-ppc
Binary files differ
diff --git a/pc-bios/openbios-sparc32 b/pc-bios/openbios-sparc32
index e288624c7e..e744e898b8 100644
--- a/pc-bios/openbios-sparc32
+++ b/pc-bios/openbios-sparc32
Binary files differ
diff --git a/pc-bios/openbios-sparc64 b/pc-bios/openbios-sparc64
index f69e56c780..4d23be3edc 100644
--- a/pc-bios/openbios-sparc64
+++ b/pc-bios/openbios-sparc64
Binary files differ
diff --git a/qemu-seccomp.c b/qemu-seccomp.c
index 2866e3c2a6..cb569dc058 100644
--- a/qemu-seccomp.c
+++ b/qemu-seccomp.c
@@ -16,11 +16,13 @@
#include <seccomp.h>
#include "sysemu/seccomp.h"
+/* For some architectures (notably ARM) cacheflush is not supported until
+ * libseccomp 2.2.3, but configure enforces that we are using a more recent
+ * version on those hosts, so it is OK for this check to be less strict.
+ */
#if SCMP_VER_MAJOR >= 3
#define HAVE_CACHEFLUSH
-#elif SCMP_VER_MAJOR == 2 && SCMP_VER_MINOR >= 3
- #define HAVE_CACHEFLUSH
-#elif SCMP_VER_MAJOR == 2 && SCMP_VER_MINOR == 2 && SCMP_VER_MICRO >= 3
+#elif SCMP_VER_MAJOR == 2 && SCMP_VER_MINOR >= 2
#define HAVE_CACHEFLUSH
#endif
@@ -250,6 +252,7 @@ static const struct QemuSeccompSyscall seccomp_whitelist[] = {
#ifdef HAVE_CACHEFLUSH
{ SCMP_SYS(cacheflush), 240 },
#endif
+ { SCMP_SYS(sysinfo), 240 },
};
int seccomp_start(void)
diff --git a/roms/openbios b/roms/openbios
-Subproject 0dbda5d935f95391d16431cd3c079fbf53d668d
+Subproject 422b916649aa0db8c5edadccb22387b3e807e3b
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index ddae932ee1..d0b5b69156 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2897,6 +2897,14 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
env->cpuid_level = 7;
}
+ if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
+ error_setg(&local_err,
+ kvm_enabled() ?
+ "Host doesn't support requested features" :
+ "TCG doesn't support requested features");
+ goto out;
+ }
+
/* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
* CPUID[1].EDX.
*/
@@ -2907,14 +2915,6 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
}
- if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
- error_setg(&local_err,
- kvm_enabled() ?
- "Host doesn't support requested features" :
- "TCG doesn't support requested features");
- goto out;
- }
-
#ifndef CONFIG_USER_ONLY
qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 9d4e43cf1f..5282533b38 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -2415,6 +2415,16 @@ static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
return msr & (1ULL << MSR_SF);
}
+/**
+ * Check whether register rx is in the range between start and
+ * start + nregs (as needed by the LSWX and LSWI instructions)
+ */
+static inline bool lsw_reg_in_range(int start, int nregs, int rx)
+{
+ return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
+ (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
+}
+
extern void (*cpu_ppc_hypercall)(PowerPCCPU *);
#include "exec/exec-all.h"
diff --git a/target-ppc/machine.c b/target-ppc/machine.c
index 692121e983..46684fb933 100644
--- a/target-ppc/machine.c
+++ b/target-ppc/machine.c
@@ -136,7 +136,7 @@ static void cpu_pre_save(void *opaque)
env->spr[SPR_LR] = env->lr;
env->spr[SPR_CTR] = env->ctr;
- env->spr[SPR_XER] = env->xer;
+ env->spr[SPR_XER] = cpu_read_xer(env);
#if defined(TARGET_PPC64)
env->spr[SPR_CFAR] = env->cfar;
#endif
diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c
index 581d9faa23..6d584c9126 100644
--- a/target-ppc/mem_helper.c
+++ b/target-ppc/mem_helper.c
@@ -102,8 +102,9 @@ void helper_lswx(CPUPPCState *env, target_ulong addr, uint32_t reg,
{
if (likely(xer_bc != 0)) {
int num_used_regs = (xer_bc + 3) / 4;
- if (unlikely((ra != 0 && reg < ra && (reg + num_used_regs) > ra) ||
- (reg < rb && (reg + num_used_regs) > rb))) {
+ if (unlikely((ra != 0 && lsw_reg_in_range(reg, num_used_regs, ra)) ||
+ lsw_reg_in_range(reg, num_used_regs, rb))) {
+ env->nip += 4; /* Compensate the "nip - 4" from gen_lswx() */
helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
POWERPC_EXCP_INVAL |
POWERPC_EXCP_INVAL_LSWX);
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 6f0e7b4fac..b3860ecdea 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -3227,10 +3227,8 @@ static void gen_lswi(DisasContext *ctx)
if (nb == 0)
nb = 32;
- nr = nb / 4;
- if (unlikely(((start + nr) > 32 &&
- start <= ra && (start + nr - 32) > ra) ||
- ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
+ nr = (nb + 3) / 4;
+ if (unlikely(lsw_reg_in_range(start, nr, ra))) {
gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
return;
}
generated by cgit v1.2.1 (git 2.18.0) at 2024-05-12 19:46:14 +0000