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-rw-r--r--target-i386/cpu.h2
-rw-r--r--target-i386/helper.c6
-rw-r--r--target-i386/machine.c9
3 files changed, 6 insertions, 11 deletions
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index f318942eec..a4acf86bbb 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -589,7 +589,7 @@ typedef struct CPUX86State {
SegmentCache idt; /* only base and limit are used */
target_ulong cr[5]; /* NOTE: cr1 is unused */
- uint64_t a20_mask;
+ int32_t a20_mask;
/* FPU state */
unsigned int fpstt; /* top of stack index */
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 8111f25662..999c1bfb14 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -780,7 +780,7 @@ void cpu_dump_state(CPUState *env, FILE *f,
eflags & CC_C ? 'C' : '-',
env->hflags & HF_CPL_MASK,
(env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
- (int)(env->a20_mask >> 20) & 1,
+ (env->a20_mask >> 20) & 1,
(env->hflags >> HF_SMM_SHIFT) & 1,
env->halted);
} else
@@ -807,7 +807,7 @@ void cpu_dump_state(CPUState *env, FILE *f,
eflags & CC_C ? 'C' : '-',
env->hflags & HF_CPL_MASK,
(env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
- (int)(env->a20_mask >> 20) & 1,
+ (env->a20_mask >> 20) & 1,
(env->hflags >> HF_SMM_SHIFT) & 1,
env->halted);
}
@@ -938,7 +938,7 @@ void cpu_x86_set_a20(CPUX86State *env, int a20_state)
/* when a20 is changed, all the MMU mappings are invalid, so
we must flush everything */
tlb_flush(env, 1);
- env->a20_mask = (~0x100000) | (a20_state << 20);
+ env->a20_mask = ~(1 << 20) | (a20_state << 20);
}
}
diff --git a/target-i386/machine.c b/target-i386/machine.c
index adbb16fb87..23c01ee409 100644
--- a/target-i386/machine.c
+++ b/target-i386/machine.c
@@ -27,7 +27,6 @@ void cpu_save(QEMUFile *f, void *opaque)
{
CPUState *env = opaque;
uint16_t fptag, fpus, fpuc, fpregs_format;
- int32_t a20_mask;
int32_t pending_irq;
int i, bit;
@@ -98,8 +97,7 @@ void cpu_save(QEMUFile *f, void *opaque)
qemu_put_betls(f, &env->dr[i]);
/* MMU */
- a20_mask = (int32_t) env->a20_mask;
- qemu_put_sbe32s(f, &a20_mask);
+ qemu_put_sbe32s(f, &env->a20_mask);
/* XMM */
qemu_put_be32s(f, &env->mxcsr);
@@ -201,7 +199,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
CPUState *env = opaque;
int i, guess_mmx;
uint16_t fpus, fpuc, fptag, fpregs_format;
- int32_t a20_mask;
int32_t pending_irq;
cpu_synchronize_state(env);
@@ -300,9 +297,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
for (i = 0; i < 4; i++)
hw_breakpoint_insert(env, i);
- /* MMU */
- qemu_get_sbe32s(f, &a20_mask);
- env->a20_mask = a20_mask;
+ qemu_get_sbe32s(f, &env->a20_mask);
qemu_get_be32s(f, &env->mxcsr);
for(i = 0; i < CPU_NB_REGS; i++) {