diff options
| -rw-r--r-- | target/riscv/translate.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 808eab7f50..c3a029afef 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -280,7 +280,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1, tcg_gen_andi_tl(source2, source2, 0x1F); tcg_gen_sar_tl(source1, source1, source2); break; - /* fall through to SRA */ #endif case OPC_RISC_SRA: tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1); |