diff options
| -rw-r--r-- | cpu-exec.c | 62 | ||||
| -rw-r--r-- | exec-all.h | 2 | ||||
| -rw-r--r-- | exec.c | 4 | ||||
| -rw-r--r-- | gdbstub.c | 66 | ||||
| -rw-r--r-- | softmmu_header.h | 6 | ||||
| -rw-r--r-- | vl.c | 2 | ||||
| -rw-r--r-- | vl.h | 3 |
7 files changed, 143 insertions, 2 deletions
diff --git a/cpu-exec.c b/cpu-exec.c index 55758faef2..d09b564af4 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -210,6 +210,10 @@ static inline TranslationBlock *tb_find_fast(void) flags = env->ps; cs_base = 0; pc = env->pc; +#elif defined(TARGET_CRIS) + flags = 0; + cs_base = 0; + pc = env->pc; #else #error unsupported CPU #endif @@ -284,6 +288,7 @@ int cpu_exec(CPUState *env1) #elif defined(TARGET_PPC) #elif defined(TARGET_MIPS) #elif defined(TARGET_SH4) +#elif defined(TARGET_CRIS) /* XXXXX */ #else #error unsupported target CPU @@ -335,6 +340,8 @@ int cpu_exec(CPUState *env1) do_interrupt(env); #elif defined(TARGET_ALPHA) do_interrupt(env); +#elif defined(TARGET_CRIS) + do_interrupt(env); #elif defined(TARGET_M68K) do_interrupt(0); #endif @@ -385,7 +392,7 @@ int cpu_exec(CPUState *env1) cpu_loop_exit(); } #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \ - defined(TARGET_PPC) || defined(TARGET_ALPHA) + defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) if (interrupt_request & CPU_INTERRUPT_HALT) { env->interrupt_request &= ~CPU_INTERRUPT_HALT; env->halted = 1; @@ -517,6 +524,11 @@ int cpu_exec(CPUState *env1) if (interrupt_request & CPU_INTERRUPT_HARD) { do_interrupt(env); } +#elif defined(TARGET_CRIS) + if (interrupt_request & CPU_INTERRUPT_HARD) { + do_interrupt(env); + env->interrupt_request &= ~CPU_INTERRUPT_HARD; + } #elif defined(TARGET_M68K) if (interrupt_request & CPU_INTERRUPT_HARD && ((env->sr & SR_I) >> SR_I_SHIFT) @@ -576,6 +588,8 @@ int cpu_exec(CPUState *env1) cpu_dump_state(env, logfile, fprintf, 0); #elif defined(TARGET_ALPHA) cpu_dump_state(env, logfile, fprintf, 0); +#elif defined(TARGET_CRIS) + cpu_dump_state(env, logfile, fprintf, 0); #else #error unsupported target CPU #endif @@ -769,6 +783,7 @@ int cpu_exec(CPUState *env1) #elif defined(TARGET_MIPS) #elif defined(TARGET_SH4) #elif defined(TARGET_ALPHA) +#elif defined(TARGET_CRIS) /* XXXXX */ #else #error unsupported target CPU @@ -1200,6 +1215,51 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address, /* never comes here */ return 1; } +#elif defined (TARGET_CRIS) +static inline int handle_cpu_signal(unsigned long pc, unsigned long address, + int is_write, sigset_t *old_set, + void *puc) +{ + TranslationBlock *tb; + int ret; + + if (cpu_single_env) + env = cpu_single_env; /* XXX: find a correct solution for multithread */ +#if defined(DEBUG_SIGNAL) + printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", + pc, address, is_write, *(unsigned long *)old_set); +#endif + /* XXX: locking issue */ + if (is_write && page_unprotect(h2g(address), pc, puc)) { + return 1; + } + + /* see if it is an MMU fault */ + ret = cpu_cris_handle_mmu_fault(env, address, is_write, 1, 0); + if (ret < 0) + return 0; /* not an MMU fault */ + if (ret == 0) + return 1; /* the MMU fault was handled without causing real CPU fault */ + + /* now we have a real cpu fault */ + tb = tb_find_pc(pc); + if (tb) { + /* the PC is inside the translated code. It means that we have + a virtual CPU fault */ + cpu_restore_state(tb, env, pc, puc); + } +#if 0 + printf("PF exception: NIP=0x%08x error=0x%x %p\n", + env->nip, env->error_code, tb); +#endif + /* we restore the process signal mask as the sigreturn should + do it (XXX: use sigsetjmp) */ + sigprocmask(SIG_SETMASK, old_set, NULL); + cpu_loop_exit(); + /* never comes here */ + return 1; +} + #else #error unsupported target CPU #endif diff --git a/exec-all.h b/exec-all.h index dc5a10d972..a01494b03d 100644 --- a/exec-all.h +++ b/exec-all.h @@ -617,6 +617,8 @@ static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) is_user = ((env->ps >> 3) & 3); #elif defined (TARGET_M68K) is_user = ((env->sr & SR_S) == 0); +#elif defined (TARGET_CRIS) + is_user = (0); #else #error unimplemented CPU #endif @@ -2066,6 +2066,8 @@ static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr) #endif #ifdef TARGET_SPARC do_unassigned_access(addr, 0, 0, 0); +#elif TARGET_CRIS + do_unassigned_access(addr, 0, 0, 0); #endif return 0; } @@ -2077,6 +2079,8 @@ static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_ #endif #ifdef TARGET_SPARC do_unassigned_access(addr, 1, 0, 0); +#elif TARGET_CRIS + do_unassigned_access(addr, 1, 0, 0); #endif } @@ -728,6 +728,66 @@ static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size) for (i = 0; i < 8; i++) LOAD(env->gregs[i]); for (i = 0; i < 8; i++) LOAD(env->gregs[i + 16]); } +#elif defined (TARGET_CRIS) + +static int cris_save_32 (unsigned char *d, uint32_t value) +{ + *d++ = (value); + *d++ = (value >>= 8); + *d++ = (value >>= 8); + *d++ = (value >>= 8); + return 4; +} +static int cris_save_16 (unsigned char *d, uint32_t value) +{ + *d++ = (value); + *d++ = (value >>= 8); + return 2; +} +static int cris_save_8 (unsigned char *d, uint32_t value) +{ + *d++ = (value); + return 1; +} + +/* FIXME: this will bug on archs not supporting unaligned word accesses. */ +static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf) +{ + uint8_t *ptr = mem_buf; + uint8_t srs; + int i; + + for (i = 0; i < 16; i++) + ptr += cris_save_32 (ptr, env->regs[i]); + + srs = env->pregs[SR_SRS]; + + ptr += cris_save_8 (ptr, env->pregs[0]); + ptr += cris_save_8 (ptr, env->pregs[1]); + ptr += cris_save_32 (ptr, env->pregs[2]); + ptr += cris_save_8 (ptr, srs); + ptr += cris_save_16 (ptr, env->pregs[4]); + + for (i = 5; i < 16; i++) + ptr += cris_save_32 (ptr, env->pregs[i]); + + ptr += cris_save_32 (ptr, env->pc); + + for (i = 0; i < 16; i++) + ptr += cris_save_32 (ptr, env->sregs[srs][i]); + + return ((uint8_t *)ptr - mem_buf); +} + +static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size) +{ + uint32_t *ptr = (uint32_t *)mem_buf; + int i; + +#define LOAD(x) (x)=*ptr++; + for (i = 0; i < 16; i++) LOAD(env->regs[i]); + LOAD (env->pc); +} #else static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf) { @@ -745,7 +805,7 @@ static int gdb_handle_packet(GDBState *s, CPUState *env, const char *line_buf) const char *p; int ch, reg_size, type; char buf[4096]; - uint8_t mem_buf[2000]; + uint8_t mem_buf[4096]; uint32_t *registers; target_ulong addr, len; @@ -776,6 +836,8 @@ static int gdb_handle_packet(GDBState *s, CPUState *env, const char *line_buf) env->pc = addr; #elif defined (TARGET_MIPS) env->PC[env->current_tc] = addr; +#elif defined (TARGET_CRIS) + env->pc = addr; #endif } #ifdef CONFIG_USER_ONLY @@ -800,6 +862,8 @@ static int gdb_handle_packet(GDBState *s, CPUState *env, const char *line_buf) env->pc = addr; #elif defined (TARGET_MIPS) env->PC[env->current_tc] = addr; +#elif defined (TARGET_CRIS) + env->pc = addr; #endif } cpu_single_step(env, 1); diff --git a/softmmu_header.h b/softmmu_header.h index 768b87781d..384518bb68 100644 --- a/softmmu_header.h +++ b/softmmu_header.h @@ -67,6 +67,9 @@ #define CPU_MEM_INDEX ((env->ps >> 3) & 3) #elif defined (TARGET_M68K) #define CPU_MEM_INDEX ((env->sr & SR_S) == 0) +#elif defined (TARGET_CRIS) +/* CRIS FIXME: I guess we want to validate supervisor mode acceses here. */ +#define CPU_MEM_INDEX (0) #else #error unsupported CPU #endif @@ -90,6 +93,9 @@ #define CPU_MEM_INDEX ((env->ps >> 3) & 3) #elif defined (TARGET_M68K) #define CPU_MEM_INDEX ((env->sr & SR_S) == 0) +#elif defined (TARGET_CRIS) +/* CRIS FIXME: I guess we want to validate supervisor mode acceses here. */ +#define CPU_MEM_INDEX (0) #else #error unsupported CPU #endif @@ -7390,6 +7390,8 @@ void register_machines(void) #elif defined(TARGET_M68K) qemu_register_machine(&mcf5208evb_machine); qemu_register_machine(&an5206_machine); +#elif defined(TARGET_CRIS) + qemu_register_machine(&bareetraxfs_machine); #else #error unsupported CPU #endif @@ -1173,6 +1173,9 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base); void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr); void acpi_bios_init(void); +/* Axis ETRAX. */ +extern QEMUMachine bareetraxfs_machine; + /* pc.c */ extern QEMUMachine pc_machine; extern QEMUMachine isapc_machine; |