diff options
| -rw-r--r-- | cpu-exec.c | 5 | ||||
| -rw-r--r-- | hw/sun4m.c | 9 | ||||
| -rw-r--r-- | target-sparc/cpu.h | 1 | ||||
| -rw-r--r-- | target-sparc/helper.c | 7 | ||||
| -rw-r--r-- | target-sparc/op_helper.c | 4 | ||||
| -rw-r--r-- | target-sparc/translate.c | 5 |
6 files changed, 21 insertions, 10 deletions
diff --git a/cpu-exec.c b/cpu-exec.c index 58737b3a40..8d91520408 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -181,8 +181,9 @@ static inline TranslationBlock *tb_find_fast(void) flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2)) | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2); #else - // FPU enable . MMU enabled . MMU no-fault . Supervisor - flags = (env->psref << 3) | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1) + // FPU enable . MMU Boot . MMU enabled . MMU no-fault . Supervisor + flags = (env->psref << 4) | (((env->mmuregs[0] & MMU_BM) >> 14) << 3) + | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1) | env->psrs; #endif cs_base = env->npc; diff --git a/hw/sun4m.c b/hw/sun4m.c index 4da4138d91..a76c53b28b 100644 --- a/hw/sun4m.c +++ b/hw/sun4m.c @@ -50,7 +50,8 @@ #define CMDLINE_ADDR 0x007ff000 #define INITRD_LOAD_ADDR 0x00800000 #define PROM_SIZE_MAX (256 * 1024) -#define PROM_ADDR 0xffd00000 +#define PROM_PADDR 0xff0000000ULL +#define PROM_VADDR 0xffd00000 #define PROM_FILENAME "openbios-sparc32" #define MAX_CPUS 16 @@ -425,12 +426,12 @@ static void sun4m_load_kernel(long vram_size, int RAM_size, int boot_device, linux_boot = (kernel_filename != NULL); prom_offset = RAM_size + vram_size; - cpu_register_physical_memory(PROM_ADDR, + cpu_register_physical_memory(PROM_PADDR, (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK, prom_offset | IO_MEM_ROM); snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAME); - ret = load_elf(buf, 0, NULL, NULL, NULL); + ret = load_elf(buf, PROM_PADDR - PROM_VADDR, NULL, NULL, NULL); if (ret < 0) { fprintf(stderr, "qemu: could not load prom '%s'\n", buf); @@ -588,7 +589,7 @@ static void ss10_init(int RAM_size, int vga_ram_size, int boot_device, cpu_model = "TI SuperSparc II"; sun4m_common_init(RAM_size, boot_device, ds, kernel_filename, kernel_cmdline, initrd_filename, cpu_model, - 1, PROM_ADDR); // XXX prom overlap, actually first 4GB ok + 1, 0xffffffff); // XXX actually first 62GB ok } QEMUMachine ss5_machine = { diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index 6f0da43b87..5c8c49ab63 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -145,6 +145,7 @@ /* MMU */ #define MMU_E (1<<0) #define MMU_NF (1<<1) +#define MMU_BM (1<<14) #define PTE_ENTRYTYPE_MASK 3 #define PTE_ACCESS_MASK 0x1c diff --git a/target-sparc/helper.c b/target-sparc/helper.c index b78e5dfb88..af8bc96948 100644 --- a/target-sparc/helper.c +++ b/target-sparc/helper.c @@ -110,7 +110,14 @@ int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot unsigned long page_offset; virt_addr = address & TARGET_PAGE_MASK; + if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ + // Boot mode: instruction fetches are taken from PROM + if (rw == 2 && (env->mmuregs[0] & MMU_BM)) { + *physical = 0xff0000000ULL | (address & 0x3ffffULL); + *prot = PAGE_READ | PAGE_EXEC; + return 0; + } *physical = address; *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; return 0; diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c index 21ae5dec2b..eea4a63771 100644 --- a/target-sparc/op_helper.c +++ b/target-sparc/op_helper.c @@ -337,8 +337,8 @@ void helper_st_asi(int asi, int size) oldreg = env->mmuregs[reg]; switch(reg) { case 0: - env->mmuregs[reg] &= ~(MMU_E | MMU_NF); - env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF); + env->mmuregs[reg] &= ~(MMU_E | MMU_NF | MMU_BM); + env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF | MMU_BM); // Mappings generated during no-fault mode or MMU // disabled mode are invalid in normal mode if (oldreg != env->mmuregs[reg]) diff --git a/target-sparc/translate.c b/target-sparc/translate.c index d617b91e99..d12a356c60 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -3486,8 +3486,9 @@ void cpu_reset(CPUSPARCState *env) env->pstate = PS_PRIV; env->pc = 0x1fff0000000ULL; #else - env->pc = 0xffd00000; + env->pc = 0; env->mmuregs[0] &= ~(MMU_E | MMU_NF); + env->mmuregs[0] |= MMU_BM; #endif env->npc = env->pc + 4; #endif @@ -3584,7 +3585,7 @@ int cpu_sparc_register (CPUSPARCState *env, const sparc_def_t *def) env->version = def->iu_version; env->fsr = def->fpu_version; #if !defined(TARGET_SPARC64) - env->mmuregs[0] = def->mmu_version; + env->mmuregs[0] |= def->mmu_version; #endif return 0; } |