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-rw-r--r--target-microblaze/cpu-qom.h2
-rw-r--r--target-microblaze/cpu.c14
-rw-r--r--target-microblaze/translate.c3
3 files changed, 17 insertions, 2 deletions
diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h
index f75549dc22..5ea911c8e4 100644
--- a/target-microblaze/cpu-qom.h
+++ b/target-microblaze/cpu-qom.h
@@ -33,6 +33,7 @@
/**
* MicroBlazeCPUClass:
+ * @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
*
* A MicroBlaze CPU model.
@@ -42,6 +43,7 @@ typedef struct MicroBlazeCPUClass {
CPUClass parent_class;
/*< public >*/
+ DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu);
} MicroBlazeCPUClass;
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index 39230fddcc..baae47b2c6 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -85,6 +85,17 @@ static void mb_cpu_reset(CPUState *s)
#endif
}
+static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+ MicroBlazeCPU *cpu = MICROBLAZE_CPU(dev);
+ MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
+
+ cpu_reset(CPU(cpu));
+ qemu_init_vcpu(&cpu->env);
+
+ mcc->parent_realize(dev, errp);
+}
+
static void mb_cpu_initfn(Object *obj)
{
MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
@@ -106,6 +117,9 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
CPUClass *cc = CPU_CLASS(oc);
MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
+ mcc->parent_realize = dc->realize;
+ dc->realize = mb_cpu_realizefn;
+
mcc->parent_reset = cc->reset;
cc->reset = mb_cpu_reset;
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 58ce71267d..a84856ba43 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -1970,8 +1970,7 @@ MicroBlazeCPU *cpu_mb_init(const char *cpu_model)
cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
- cpu_reset(CPU(cpu));
- qemu_init_vcpu(&cpu->env);
+ object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
if (tcg_initialized) {
return cpu;