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-rw-r--r--include/exec/gen-icount.h6
-rw-r--r--target-alpha/translate.c2
-rw-r--r--target-arm/translate-a64.c2
-rw-r--r--target-arm/translate.c2
-rw-r--r--target-cris/translate.c2
-rw-r--r--target-i386/translate.c2
-rw-r--r--target-lm32/translate.c2
-rw-r--r--target-m68k/translate.c2
-rw-r--r--target-microblaze/translate.c2
-rw-r--r--target-mips/translate.c2
-rw-r--r--target-moxie/translate.c2
-rw-r--r--target-openrisc/translate.c2
-rw-r--r--target-ppc/translate.c2
-rw-r--r--target-s390x/translate.c2
-rw-r--r--target-sh4/translate.c2
-rw-r--r--target-sparc/translate.c2
-rw-r--r--target-tricore/translate.c2
-rw-r--r--target-unicore32/translate.c2
-rw-r--r--target-xtensa/translate.c2
19 files changed, 21 insertions, 21 deletions
diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h
index da53395de6..221aad0bfd 100644
--- a/include/exec/gen-icount.h
+++ b/include/exec/gen-icount.h
@@ -9,7 +9,7 @@ static TCGArg *icount_arg;
static int icount_label;
static int exitreq_label;
-static inline void gen_tb_start(void)
+static inline void gen_tb_start(TranslationBlock *tb)
{
TCGv_i32 count;
TCGv_i32 flag;
@@ -21,7 +21,7 @@ static inline void gen_tb_start(void)
tcg_gen_brcondi_i32(TCG_COND_NE, flag, 0, exitreq_label);
tcg_temp_free_i32(flag);
- if (!use_icount)
+ if (!(tb->cflags & CF_USE_ICOUNT))
return;
icount_label = gen_new_label();
@@ -43,7 +43,7 @@ static void gen_tb_end(TranslationBlock *tb, int num_insns)
gen_set_label(exitreq_label);
tcg_gen_exit_tb((uintptr_t)tb + TB_EXIT_REQUESTED);
- if (use_icount) {
+ if (tb->cflags & CF_USE_ICOUNT) {
*icount_arg = num_insns;
gen_set_label(icount_label);
tcg_gen_exit_tb((uintptr_t)tb + TB_EXIT_ICOUNT_EXPIRED);
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 5387b93084..f8883672a8 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -2828,7 +2828,7 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu,
pc_mask = ~TARGET_PAGE_MASK;
}
- gen_tb_start();
+ gen_tb_start(tb);
do {
if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index c78ebde440..80d23597c7 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -10962,7 +10962,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
max_insns = CF_COUNT_MASK;
}
- gen_tb_start();
+ gen_tb_start(tb);
tcg_clear_temp_count();
diff --git a/target-arm/translate.c b/target-arm/translate.c
index f5a8482fbe..bdfcdf169c 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -11080,7 +11080,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
if (max_insns == 0)
max_insns = CF_COUNT_MASK;
- gen_tb_start();
+ gen_tb_start(tb);
tcg_clear_temp_count();
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 76406af980..b675ed0b18 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -3202,7 +3202,7 @@ gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,
max_insns = CF_COUNT_MASK;
}
- gen_tb_start();
+ gen_tb_start(tb);
do {
check_breakpoint(env, dc);
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 0792bd0bbe..ebdc3500e5 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -8002,7 +8002,7 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu,
if (max_insns == 0)
max_insns = CF_COUNT_MASK;
- gen_tb_start();
+ gen_tb_start(tb);
for(;;) {
if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index f748f96ebb..a7579dc8be 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/translate.c
@@ -1095,7 +1095,7 @@ void gen_intermediate_code_internal(LM32CPU *cpu,
max_insns = CF_COUNT_MASK;
}
- gen_tb_start();
+ gen_tb_start(tb);
do {
check_breakpoint(env, dc);
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index efd4cfc3c7..47edc7ae51 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -3010,7 +3010,7 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
if (max_insns == 0)
max_insns = CF_COUNT_MASK;
- gen_tb_start();
+ gen_tb_start(tb);
do {
pc_offset = dc->pc - pc_start;
gen_throws_exception = NULL;
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index fd2b771645..69ce4df4a3 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -1720,7 +1720,7 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb,
if (max_insns == 0)
max_insns = CF_COUNT_MASK;
- gen_tb_start();
+ gen_tb_start(tb);
do
{
#if SIM_COMPAT
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 2fcd330c41..e9d86b2364 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -19130,7 +19130,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
if (max_insns == 0)
max_insns = CF_COUNT_MASK;
LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags);
- gen_tb_start();
+ gen_tb_start(tb);
while (ctx.bstate == BS_NONE) {
if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
diff --git a/target-moxie/translate.c b/target-moxie/translate.c
index 4541b9bff4..564f3eedaf 100644
--- a/target-moxie/translate.c
+++ b/target-moxie/translate.c
@@ -843,7 +843,7 @@ gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb,
ctx.bstate = BS_NONE;
num_insns = 0;
- gen_tb_start();
+ gen_tb_start(tb);
do {
if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 407bd9762f..7dea405c69 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -1675,7 +1675,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
max_insns = CF_COUNT_MASK;
}
- gen_tb_start();
+ gen_tb_start(tb);
do {
check_breakpoint(cpu, dc);
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index f22a11695c..2e32e8d8b8 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -11329,7 +11329,7 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
if (max_insns == 0)
max_insns = CF_COUNT_MASK;
- gen_tb_start();
+ gen_tb_start(tb);
tcg_clear_temp_count();
/* Set env in case of segfault during code fetch */
while (ctx.exception == POWERPC_EXCP_NONE
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index dbf1993d46..ab01bc004e 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -4779,7 +4779,7 @@ static inline void gen_intermediate_code_internal(S390CPU *cpu,
max_insns = CF_COUNT_MASK;
}
- gen_tb_start();
+ gen_tb_start(tb);
do {
if (search_pc) {
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 3088edc6a6..7010740b21 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -1890,7 +1890,7 @@ gen_intermediate_code_internal(SuperHCPU *cpu, TranslationBlock *tb,
max_insns = tb->cflags & CF_COUNT_MASK;
if (max_insns == 0)
max_insns = CF_COUNT_MASK;
- gen_tb_start();
+ gen_tb_start(tb);
while (ctx.bstate == BS_NONE && tcg_ctx.gen_opc_ptr < gen_opc_end) {
if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 78c4e21cff..25d1bd6988 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -5271,7 +5271,7 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu,
max_insns = tb->cflags & CF_COUNT_MASK;
if (max_insns == 0)
max_insns = CF_COUNT_MASK;
- gen_tb_start();
+ gen_tb_start(tb);
do {
if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 65abf453f0..f57eb7e9c1 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -4069,7 +4069,7 @@ gen_intermediate_code_internal(TriCoreCPU *cpu, struct TranslationBlock *tb,
ctx.mem_idx = cpu_mmu_index(env);
tcg_clear_temp_count();
- gen_tb_start();
+ gen_tb_start(tb);
while (ctx.bstate == BS_NONE) {
ctx.opcode = cpu_ldl_code(env, ctx.pc);
decode_opc(env, &ctx, 0);
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index 653c225187..ab7e96f937 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -1917,7 +1917,7 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu,
}
#endif
- gen_tb_start();
+ gen_tb_start(tb);
do {
if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 65005546d6..9e137fe5ec 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -3054,7 +3054,7 @@ void gen_intermediate_code_internal(XtensaCPU *cpu,
dc.next_icount = tcg_temp_local_new_i32();
}
- gen_tb_start();
+ gen_tb_start(tb);
if (tb->flags & XTENSA_TBFLAG_EXCEPTION) {
tcg_gen_movi_i32(cpu_pc, dc.pc);
generated by cgit v1.2.1 (git 2.18.0) at 2024-06-30 18:59:30 +0000