diff options
-rw-r--r-- | hw/char/cadence_uart.c | 3 | ||||
-rw-r--r-- | target-i386/cpu.c | 16 |
2 files changed, 11 insertions, 8 deletions
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index 486591bf07..797787823e 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -375,6 +375,9 @@ static void uart_write(void *opaque, hwaddr offset, DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value); offset >>= 2; + if (offset >= CADENCE_UART_R_MAX) { + return; + } switch (offset) { case R_IER: /* ier (wts imr) */ s->r[R_IMR] |= value; diff --git a/target-i386/cpu.c b/target-i386/cpu.c index ddae932ee1..d0b5b69156 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2897,6 +2897,14 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) env->cpuid_level = 7; } + if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) { + error_setg(&local_err, + kvm_enabled() ? + "Host doesn't support requested features" : + "TCG doesn't support requested features"); + goto out; + } + /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on * CPUID[1].EDX. */ @@ -2907,14 +2915,6 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) } - if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) { - error_setg(&local_err, - kvm_enabled() ? - "Host doesn't support requested features" : - "TCG doesn't support requested features"); - goto out; - } - #ifndef CONFIG_USER_ONLY qemu_register_reset(x86_cpu_machine_reset_cb, cpu); |