diff options
| -rw-r--r-- | target-openrisc/cpu.c | 13 | ||||
| -rw-r--r-- | target-openrisc/cpu.h | 4 |
2 files changed, 12 insertions, 5 deletions
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c index a7a8de8a37..d8cc533efe 100644 --- a/target-openrisc/cpu.c +++ b/target-openrisc/cpu.c @@ -62,12 +62,15 @@ static inline void set_feature(OpenRISCCPU *cpu, int feature) cpu->env.cpucfgr = cpu->feature; } -void openrisc_cpu_realize(Object *obj, Error **errp) +static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) { - OpenRISCCPU *cpu = OPENRISC_CPU(obj); + OpenRISCCPU *cpu = OPENRISC_CPU(dev); + OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev); qemu_init_vcpu(&cpu->env); cpu_reset(CPU(cpu)); + + occ->parent_realize(dev, errp); } static void openrisc_cpu_initfn(Object *obj) @@ -134,6 +137,10 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) { OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc); CPUClass *cc = CPU_CLASS(occ); + DeviceClass *dc = DEVICE_CLASS(oc); + + occ->parent_realize = dc->realize; + dc->realize = openrisc_cpu_realizefn; occ->parent_reset = cc->reset; cc->reset = openrisc_cpu_reset; @@ -187,7 +194,7 @@ OpenRISCCPU *cpu_openrisc_init(const char *cpu_model) cpu = OPENRISC_CPU(object_new(object_class_get_name(oc))); cpu->env.cpu_model_str = cpu_model; - openrisc_cpu_realize(OBJECT(cpu), NULL); + object_property_set_bool(OBJECT(cpu), true, "realized", NULL); return cpu; } diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index 3beab45c3c..419f007991 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -33,7 +33,6 @@ struct OpenRISCCPU; #include "exec/cpu-defs.h" #include "fpu/softfloat.h" #include "qom/cpu.h" -#include "qapi/error.h" #define TYPE_OPENRISC_CPU "or32-cpu" @@ -46,6 +45,7 @@ struct OpenRISCCPU; /** * OpenRISCCPUClass: + * @parent_realize: The parent class' realize handler. * @parent_reset: The parent class' reset handler. * * A OpenRISC CPU model. @@ -55,6 +55,7 @@ typedef struct OpenRISCCPUClass { CPUClass parent_class; /*< public >*/ + DeviceRealize parent_realize; void (*parent_reset)(CPUState *cpu); } OpenRISCCPUClass; @@ -340,7 +341,6 @@ static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env) #define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e)) OpenRISCCPU *cpu_openrisc_init(const char *cpu_model); -void openrisc_cpu_realize(Object *obj, Error **errp); void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf); int cpu_openrisc_exec(CPUOpenRISCState *s); |