diff options
Diffstat (limited to 'hw/pci-host/q35.c')
-rw-r--r-- | hw/pci-host/q35.c | 68 |
1 files changed, 35 insertions, 33 deletions
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 8c3ee535ff..6b1b3b7ab1 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -34,33 +34,27 @@ * Q35 host */ -static int q35_host_init(SysBusDevice *dev) +static void q35_host_realize(DeviceState *dev, Error **errp) { - PCIBus *b; - PCIHostState *pci = FROM_SYSBUS(PCIHostState, dev); - Q35PCIHost *s = Q35_HOST_DEVICE(&dev->qdev); + PCIHostState *pci = PCI_HOST_BRIDGE(dev); + Q35PCIHost *s = Q35_HOST_DEVICE(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); - memory_region_init_io(&pci->conf_mem, OBJECT(pci), &pci_host_conf_le_ops, pci, - "pci-conf-idx", 4); - sysbus_add_io(dev, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); - sysbus_init_ioports(&pci->busdev, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); + sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); + sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); - memory_region_init_io(&pci->data_mem, OBJECT(pci), &pci_host_data_le_ops, pci, - "pci-conf-data", 4); - sysbus_add_io(dev, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); - sysbus_init_ioports(&pci->busdev, MCH_HOST_BRIDGE_CONFIG_DATA, 4); + sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); + sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); - if (pcie_host_init(&s->host) < 0) { - return -1; + if (pcie_host_init(PCIE_HOST_BRIDGE(s)) < 0) { + error_setg(errp, "failed to initialize pcie host"); + return; } - b = pci_bus_new(&s->host.pci.busdev.qdev, "pcie.0", - s->mch.pci_address_space, s->mch.address_space_io, - 0, TYPE_PCIE_BUS); - s->host.pci.bus = b; - qdev_set_parent_bus(DEVICE(&s->mch), BUS(b)); + pci->bus = pci_bus_new(DEVICE(s), "pcie.0", + s->mch.pci_address_space, s->mch.address_space_io, + 0, TYPE_PCIE_BUS); + qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus)); qdev_init_nofail(DEVICE(&s->mch)); - - return 0; } static const char *q35_host_root_bus_path(PCIHostState *host_bridge, @@ -71,7 +65,7 @@ static const char *q35_host_root_bus_path(PCIHostState *host_bridge, } static Property mch_props[] = { - DEFINE_PROP_UINT64("MCFG", Q35PCIHost, host.base_addr, + DEFINE_PROP_UINT64("MCFG", Q35PCIHost, parent_obj.base_addr, MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), DEFINE_PROP_END_OF_LIST(), }; @@ -79,11 +73,10 @@ static Property mch_props[] = { static void q35_host_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); - SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); hc->root_bus_path = q35_host_root_bus_path; - k->init = q35_host_init; + dc->realize = q35_host_realize; dc->props = mch_props; dc->fw_name = "pci"; } @@ -91,6 +84,12 @@ static void q35_host_class_init(ObjectClass *klass, void *data) static void q35_host_initfn(Object *obj) { Q35PCIHost *s = Q35_HOST_DEVICE(obj); + PCIHostState *phb = PCI_HOST_BRIDGE(obj); + + memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, + "pci-conf-idx", 4); + memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, + "pci-conf-data", 4); object_initialize(&s->mch, TYPE_MCH_PCI_DEVICE); object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL); @@ -113,10 +112,9 @@ static const TypeInfo q35_host_info = { /* PCIe MMCFG */ static void mch_update_pciexbar(MCHPCIState *mch) { - PCIDevice *pci_dev = &mch->d; - BusState *bus = qdev_get_parent_bus(&pci_dev->qdev); - DeviceState *qdev = bus->parent; - Q35PCIHost *s = Q35_HOST_DEVICE(qdev); + PCIDevice *pci_dev = PCI_DEVICE(mch); + BusState *bus = qdev_get_parent_bus(DEVICE(mch)); + PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent); uint64_t pciexbar; int enable; @@ -148,18 +146,19 @@ static void mch_update_pciexbar(MCHPCIState *mch) break; } addr = pciexbar & addr_mask; - pcie_host_mmcfg_update(&s->host, enable, addr, length); + pcie_host_mmcfg_update(pehb, enable, addr, length); } /* PAM */ static void mch_update_pam(MCHPCIState *mch) { + PCIDevice *pd = PCI_DEVICE(mch); int i; memory_region_transaction_begin(); for (i = 0; i < 13; i++) { pam_update(&mch->pam_regions[i], i, - mch->d.config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]); + pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]); } memory_region_transaction_commit(); } @@ -167,8 +166,10 @@ static void mch_update_pam(MCHPCIState *mch) /* SMRAM */ static void mch_update_smram(MCHPCIState *mch) { + PCIDevice *pd = PCI_DEVICE(mch); + memory_region_transaction_begin(); - smram_update(&mch->smram_region, mch->d.config[MCH_HOST_BRDIGE_SMRAM], + smram_update(&mch->smram_region, pd->config[MCH_HOST_BRDIGE_SMRAM], mch->smm_enabled); memory_region_transaction_commit(); } @@ -176,9 +177,10 @@ static void mch_update_smram(MCHPCIState *mch) static void mch_set_smm(int smm, void *arg) { MCHPCIState *mch = arg; + PCIDevice *pd = PCI_DEVICE(mch); memory_region_transaction_begin(); - smram_set_smm(&mch->smm_enabled, smm, mch->d.config[MCH_HOST_BRDIGE_SMRAM], + smram_set_smm(&mch->smm_enabled, smm, pd->config[MCH_HOST_BRDIGE_SMRAM], &mch->smram_region); memory_region_transaction_commit(); } @@ -228,7 +230,7 @@ static const VMStateDescription vmstate_mch = { .minimum_version_id_old = 1, .post_load = mch_post_load, .fields = (VMStateField []) { - VMSTATE_PCI_DEVICE(d, MCHPCIState), + VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), VMSTATE_UINT8(smm_enabled, MCHPCIState), VMSTATE_END_OF_LIST() } |