diff options
Diffstat (limited to 'hw/pci-host')
| -rw-r--r-- | hw/pci-host/piix.c | 9 | ||||
| -rw-r--r-- | hw/pci-host/q35.c | 17 |
2 files changed, 26 insertions, 0 deletions
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c index 2ab1599b5a..870e38810c 100644 --- a/hw/pci-host/piix.c +++ b/hw/pci-host/piix.c @@ -630,11 +630,20 @@ static const TypeInfo i440fx_info = { .class_init = i440fx_class_init, }; +static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge, + PCIBus *rootbus) +{ + /* For backwards compat with old device paths */ + return "0000"; +} + static void i440fx_pcihost_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); + hc->root_bus_path = i440fx_pcihost_root_bus_path; k->init = i440fx_pcihost_initfn; dc->fw_name = "pci"; dc->no_user = 1; diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 5661ace80c..8c3ee535ff 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -63,6 +63,13 @@ static int q35_host_init(SysBusDevice *dev) return 0; } +static const char *q35_host_root_bus_path(PCIHostState *host_bridge, + PCIBus *rootbus) +{ + /* For backwards compat with old device paths */ + return "0000"; +} + static Property mch_props[] = { DEFINE_PROP_UINT64("MCFG", Q35PCIHost, host.base_addr, MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), @@ -73,7 +80,9 @@ static void q35_host_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); + hc->root_bus_path = q35_host_root_bus_path; k->init = q35_host_init; dc->props = mch_props; dc->fw_name = "pci"; @@ -244,6 +253,14 @@ static int mch_init(PCIDevice *d) hwaddr pci_hole64_size; MCHPCIState *mch = MCH_PCI_DEVICE(d); + /* Leave enough space for the biggest MCFG BAR */ + /* TODO: this matches current bios behaviour, but + * it's not a power of two, which means an MTRR + * can't cover it exactly. + */ + mch->guest_info->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT + + MCH_HOST_BRIDGE_PCIEXBAR_MAX; + /* setup pci memory regions */ memory_region_init_alias(&mch->pci_hole, OBJECT(mch), "pci-hole", mch->pci_address_space, |