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-rw-r--r--hw/dec_pci.c6
-rw-r--r--hw/grackle_pci.c6
-rw-r--r--hw/pci_host.c105
-rw-r--r--hw/pci_host.h6
-rw-r--r--hw/ppce500_pci.c6
-rw-r--r--hw/unin_pci.c18
6 files changed, 46 insertions, 101 deletions
diff --git a/hw/dec_pci.c b/hw/dec_pci.c
index aa07ab7d84..bf88f2ac80 100644
--- a/hw/dec_pci.c
+++ b/hw/dec_pci.c
@@ -96,8 +96,10 @@ static int pci_dec_21154_init_device(SysBusDevice *dev)
s = FROM_SYSBUS(DECState, dev);
- pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
- pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
+ pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
+ DEVICE_LITTLE_ENDIAN);
+ pci_mem_data = pci_host_data_register_mmio(&s->host_state,
+ DEVICE_LITTLE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
return 0;
diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c
index 91c755f4d7..bd3d6b0d9f 100644
--- a/hw/grackle_pci.c
+++ b/hw/grackle_pci.c
@@ -108,8 +108,10 @@ static int pci_grackle_init_device(SysBusDevice *dev)
s = FROM_SYSBUS(GrackleState, dev);
- pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
- pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
+ pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
+ DEVICE_LITTLE_ENDIAN);
+ pci_mem_data = pci_host_data_register_mmio(&s->host_state,
+ DEVICE_LITTLE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
diff --git a/hw/pci_host.c b/hw/pci_host.c
index a6e39c915c..eebff7ab92 100644
--- a/hw/pci_host.c
+++ b/hw/pci_host.c
@@ -78,64 +78,39 @@ uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len)
return val;
}
-static void pci_host_config_write_swap(ReadWriteHandler *handler,
- pcibus_t addr, uint32_t val, int len)
+static void pci_host_config_write(ReadWriteHandler *handler,
+ pcibus_t addr, uint32_t val, int len)
{
PCIHostState *s = container_of(handler, PCIHostState, conf_handler);
PCI_DPRINTF("%s addr %" FMT_PCIBUS " %d val %"PRIx32"\n",
__func__, addr, len, val);
- val = qemu_bswap_len(val, len);
s->config_reg = val;
}
-static uint32_t pci_host_config_read_swap(ReadWriteHandler *handler,
- pcibus_t addr, int len)
+static uint32_t pci_host_config_read(ReadWriteHandler *handler,
+ pcibus_t addr, int len)
{
PCIHostState *s = container_of(handler, PCIHostState, conf_handler);
uint32_t val = s->config_reg;
- val = qemu_bswap_len(val, len);
PCI_DPRINTF("%s addr %" FMT_PCIBUS " len %d val %"PRIx32"\n",
__func__, addr, len, val);
return val;
}
-static void pci_host_config_write_noswap(ReadWriteHandler *handler,
- pcibus_t addr, uint32_t val, int len)
-{
- PCIHostState *s = container_of(handler, PCIHostState, conf_noswap_handler);
-
- PCI_DPRINTF("%s addr %" FMT_PCIBUS " %d val %"PRIx32"\n",
- __func__, addr, len, val);
- s->config_reg = val;
-}
-
-static uint32_t pci_host_config_read_noswap(ReadWriteHandler *handler,
- pcibus_t addr, int len)
-{
- PCIHostState *s = container_of(handler, PCIHostState, conf_noswap_handler);
- uint32_t val = s->config_reg;
-
- PCI_DPRINTF("%s addr %" FMT_PCIBUS " len %d val %"PRIx32"\n",
- __func__, addr, len, val);
- return val;
-}
-
-static void pci_host_data_write_swap(ReadWriteHandler *handler,
- pcibus_t addr, uint32_t val, int len)
+static void pci_host_data_write(ReadWriteHandler *handler,
+ pcibus_t addr, uint32_t val, int len)
{
PCIHostState *s = container_of(handler, PCIHostState, data_handler);
-
- val = qemu_bswap_len(val, len);
PCI_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n",
addr, len, val);
if (s->config_reg & (1u << 31))
pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
}
-static uint32_t pci_host_data_read_swap(ReadWriteHandler *handler,
- pcibus_t addr, int len)
+static uint32_t pci_host_data_read(ReadWriteHandler *handler,
+ pcibus_t addr, int len)
{
PCIHostState *s = container_of(handler, PCIHostState, data_handler);
uint32_t val;
@@ -144,79 +119,39 @@ static uint32_t pci_host_data_read_swap(ReadWriteHandler *handler,
val = pci_data_read(s->bus, s->config_reg | (addr & 3), len);
PCI_DPRINTF("read addr %" FMT_PCIBUS " len %d val %x\n",
addr, len, val);
- val = qemu_bswap_len(val, len);
- return val;
-}
-
-static void pci_host_data_write_noswap(ReadWriteHandler *handler,
- pcibus_t addr, uint32_t val, int len)
-{
- PCIHostState *s = container_of(handler, PCIHostState, data_noswap_handler);
- PCI_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n",
- addr, len, val);
- if (s->config_reg & (1u << 31))
- pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
-}
-
-static uint32_t pci_host_data_read_noswap(ReadWriteHandler *handler,
- pcibus_t addr, int len)
-{
- PCIHostState *s = container_of(handler, PCIHostState, data_noswap_handler);
- uint32_t val;
- if (!(s->config_reg & (1 << 31)))
- return 0xffffffff;
- val = pci_data_read(s->bus, s->config_reg | (addr & 3), len);
- PCI_DPRINTF("read addr %" FMT_PCIBUS " len %d val %x\n",
- addr, len, val);
return val;
}
static void pci_host_init(PCIHostState *s)
{
- s->conf_handler.write = pci_host_config_write_swap;
- s->conf_handler.read = pci_host_config_read_swap;
- s->conf_noswap_handler.write = pci_host_config_write_noswap;
- s->conf_noswap_handler.read = pci_host_config_read_noswap;
- s->data_handler.write = pci_host_data_write_swap;
- s->data_handler.read = pci_host_data_read_swap;
- s->data_noswap_handler.write = pci_host_data_write_noswap;
- s->data_noswap_handler.read = pci_host_data_read_noswap;
+ s->conf_handler.write = pci_host_config_write;
+ s->conf_handler.read = pci_host_config_read;
+ s->data_handler.write = pci_host_data_write;
+ s->data_handler.read = pci_host_data_read;
}
-int pci_host_conf_register_mmio(PCIHostState *s, int swap)
+int pci_host_conf_register_mmio(PCIHostState *s, int endian)
{
pci_host_init(s);
- if (swap) {
- return cpu_register_io_memory_simple(&s->conf_handler,
- DEVICE_NATIVE_ENDIAN);
- } else {
- return cpu_register_io_memory_simple(&s->conf_noswap_handler,
- DEVICE_NATIVE_ENDIAN);
- }
+ return cpu_register_io_memory_simple(&s->conf_handler, endian);
}
void pci_host_conf_register_ioport(pio_addr_t ioport, PCIHostState *s)
{
pci_host_init(s);
- register_ioport_simple(&s->conf_noswap_handler, ioport, 4, 4);
+ register_ioport_simple(&s->conf_handler, ioport, 4, 4);
}
-int pci_host_data_register_mmio(PCIHostState *s, int swap)
+int pci_host_data_register_mmio(PCIHostState *s, int endian)
{
pci_host_init(s);
- if (swap) {
- return cpu_register_io_memory_simple(&s->data_handler,
- DEVICE_NATIVE_ENDIAN);
- } else {
- return cpu_register_io_memory_simple(&s->data_noswap_handler,
- DEVICE_NATIVE_ENDIAN);
- }
+ return cpu_register_io_memory_simple(&s->data_handler, endian);
}
void pci_host_data_register_ioport(pio_addr_t ioport, PCIHostState *s)
{
pci_host_init(s);
- register_ioport_simple(&s->data_noswap_handler, ioport, 4, 1);
- register_ioport_simple(&s->data_noswap_handler, ioport, 4, 2);
- register_ioport_simple(&s->data_noswap_handler, ioport, 4, 4);
+ register_ioport_simple(&s->data_handler, ioport, 4, 1);
+ register_ioport_simple(&s->data_handler, ioport, 4, 2);
+ register_ioport_simple(&s->data_handler, ioport, 4, 4);
}
diff --git a/hw/pci_host.h b/hw/pci_host.h
index bd8ede8b72..0a585951e0 100644
--- a/hw/pci_host.h
+++ b/hw/pci_host.h
@@ -33,9 +33,7 @@
struct PCIHostState {
SysBusDevice busdev;
- ReadWriteHandler conf_noswap_handler;
ReadWriteHandler conf_handler;
- ReadWriteHandler data_noswap_handler;
ReadWriteHandler data_handler;
uint32_t config_reg;
PCIBus *bus;
@@ -45,8 +43,8 @@ void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len);
uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len);
/* for mmio */
-int pci_host_conf_register_mmio(PCIHostState *s, int swap);
-int pci_host_data_register_mmio(PCIHostState *s, int swap);
+int pci_host_conf_register_mmio(PCIHostState *s, int endian);
+int pci_host_data_register_mmio(PCIHostState *s, int endian);
/* for ioio */
void pci_host_conf_register_ioport(pio_addr_t ioport, PCIHostState *s);
diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c
index 71302ba705..11edd03f16 100644
--- a/hw/ppce500_pci.c
+++ b/hw/ppce500_pci.c
@@ -292,13 +292,15 @@ PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4], target_phys_addr_t registers)
controller->pci_dev = d;
/* CFGADDR */
- index = pci_host_conf_register_mmio(&controller->pci_state, 0);
+ index = pci_host_conf_register_mmio(&controller->pci_state,
+ DEVICE_BIG_ENDIAN);
if (index < 0)
goto free;
cpu_register_physical_memory(registers + PCIE500_CFGADDR, 4, index);
/* CFGDATA */
- index = pci_host_data_register_mmio(&controller->pci_state, 0);
+ index = pci_host_data_register_mmio(&controller->pci_state,
+ DEVICE_BIG_ENDIAN);
if (index < 0)
goto free;
cpu_register_physical_memory(registers + PCIE500_CFGDATA, 4, index);
diff --git a/hw/unin_pci.c b/hw/unin_pci.c
index 53791dd070..f2e440e901 100644
--- a/hw/unin_pci.c
+++ b/hw/unin_pci.c
@@ -151,7 +151,8 @@ static int pci_unin_main_init_device(SysBusDevice *dev)
/* Uninorth main bus */
s = FROM_SYSBUS(UNINState, dev);
- pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
+ pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
+ DEVICE_LITTLE_ENDIAN);
s->data_handler.read = unin_data_read;
s->data_handler.write = unin_data_write;
pci_mem_data = cpu_register_io_memory_simple(&s->data_handler,
@@ -173,7 +174,8 @@ static int pci_u3_agp_init_device(SysBusDevice *dev)
/* Uninorth U3 AGP bus */
s = FROM_SYSBUS(UNINState, dev);
- pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
+ pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
+ DEVICE_LITTLE_ENDIAN);
s->data_handler.read = unin_data_read;
s->data_handler.write = unin_data_write;
pci_mem_data = cpu_register_io_memory_simple(&s->data_handler,
@@ -196,8 +198,10 @@ static int pci_unin_agp_init_device(SysBusDevice *dev)
/* Uninorth AGP bus */
s = FROM_SYSBUS(UNINState, dev);
- pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 0);
- pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
+ pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
+ DEVICE_LITTLE_ENDIAN);
+ pci_mem_data = pci_host_data_register_mmio(&s->host_state,
+ DEVICE_LITTLE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
return 0;
@@ -211,8 +215,10 @@ static int pci_unin_internal_init_device(SysBusDevice *dev)
/* Uninorth internal bus */
s = FROM_SYSBUS(UNINState, dev);
- pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 0);
- pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
+ pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
+ DEVICE_LITTLE_ENDIAN);
+ pci_mem_data = pci_host_data_register_mmio(&s->host_state,
+ DEVICE_LITTLE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
return 0;
generated by cgit v1.2.1 (git 2.18.0) at 2024-06-30 18:10:54 +0000