summaryrefslogtreecommitdiff
path: root/target-i386/smm_helper.c
diff options
context:
space:
mode:
Diffstat (limited to 'target-i386/smm_helper.c')
-rw-r--r--target-i386/smm_helper.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c
index e7bb5be521..4dd6a2c544 100644
--- a/target-i386/smm_helper.c
+++ b/target-i386/smm_helper.c
@@ -99,6 +99,10 @@ void do_smm_enter(X86CPU *cpu)
x86_stl_phys(cs, sm_state + 0x7e94, env->tr.limit);
x86_stw_phys(cs, sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
+ /* ??? Vol 1, 16.5.6 Intel MPX and SMM says that IA32_BNDCFGS
+ is saved at offset 7ED0. Vol 3, 34.4.1.1, Table 32-2, has
+ 7EA0-7ED7 as "reserved". What's this, and what's really
+ supposed to happen? */
x86_stq_phys(cs, sm_state + 0x7ed0, env->efer);
x86_stq_phys(cs, sm_state + 0x7ff8, env->regs[R_EAX]);