diff options
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/cpu.h | 19 | ||||
| -rw-r--r-- | target-ppc/exec.h | 15 | ||||
| -rw-r--r-- | target-ppc/helper_regs.h | 2 | ||||
| -rw-r--r-- | target-ppc/translate.c | 6 |
4 files changed, 21 insertions, 21 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index c7291ed90c..0de7653d17 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -27,13 +27,11 @@ #if defined (TARGET_PPC64) /* PowerPC 64 definitions */ -typedef uint64_t ppc_gpr_t; #define TARGET_LONG_BITS 64 #define TARGET_PAGE_BITS 12 #else /* defined (TARGET_PPC64) */ /* PowerPC 32 definitions */ -typedef uint32_t ppc_gpr_t; #define TARGET_LONG_BITS 32 #if defined(TARGET_PPCEMB) @@ -531,19 +529,22 @@ struct CPUPPCState { /* First are the most commonly used resources * during translated code execution */ -#if (TARGET_LONG_BITS > HOST_LONG_BITS) || !defined(TARGET_PPC64) +#if TARGET_LONG_BITS > HOST_LONG_BITS + target_ulong t0, t1, t2; +#endif +#if !defined(TARGET_PPC64) /* temporary fixed-point registers - * used to emulate 64 bits registers on 32 bits hosts + * used to emulate 64 bits registers on 32 bits targets */ - uint64_t t0, t1, t2; + uint64_t t0_64, t1_64, t2_64; #endif ppc_avr_t avr0, avr1, avr2; /* general purpose registers */ - ppc_gpr_t gpr[32]; + target_ulong gpr[32]; #if !defined(TARGET_PPC64) /* Storage for GPR MSB, used by the SPE extension */ - ppc_gpr_t gprh[32]; + target_ulong gprh[32]; #endif /* LR */ target_ulong lr; @@ -561,7 +562,7 @@ struct CPUPPCState { /* machine state register */ target_ulong msr; /* temporary general purpose registers */ - ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */ + target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */ /* Floating point execution context */ /* temporary float registers */ @@ -614,7 +615,7 @@ struct CPUPPCState { ppc_avr_t avr[32]; uint32_t vscr; /* SPE registers */ - ppc_gpr_t spe_acc; + target_ulong spe_acc; float_status spe_status; uint32_t spe_fscr; diff --git a/target-ppc/exec.h b/target-ppc/exec.h index 76fdb0b1d6..2b1cfe2586 100644 --- a/target-ppc/exec.h +++ b/target-ppc/exec.h @@ -39,17 +39,16 @@ register struct CPUPPCState *env asm(AREG0); #define T2 (env->t2) #define TDX "%016" PRIx64 #else -register unsigned long T0 asm(AREG1); -register unsigned long T1 asm(AREG2); -register unsigned long T2 asm(AREG3); +register target_ulong T0 asm(AREG1); +register target_ulong T1 asm(AREG2); +register target_ulong T2 asm(AREG3); #define TDX "%016lx" #endif /* We may, sometime, need 64 bits registers on 32 bits targets */ -#if (HOST_LONG_BITS == 32) -/* no registers can be used */ -#define T0_64 (env->t0) -#define T1_64 (env->t1) -#define T2_64 (env->t2) +#if !defined(TARGET_PPC64) +#define T0_64 (env->t0_64) +#define T1_64 (env->t1_64) +#define T2_64 (env->t2_64) #else #define T0_64 T0 #define T1_64 T1 diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h index c507d26cfd..34dfa02a5e 100644 --- a/target-ppc/helper_regs.h +++ b/target-ppc/helper_regs.h @@ -42,7 +42,7 @@ static always_inline void hreg_store_xer (CPUPPCState *env, target_ulong value) /* Swap temporary saved registers with GPRs */ static always_inline void hreg_swap_gpr_tgpr (CPUPPCState *env) { - ppc_gpr_t tmp; + target_ulong tmp; tmp = env->gpr[0]; env->gpr[0] = env->tgpr[0]; diff --git a/target-ppc/translate.c b/target-ppc/translate.c index beb45c2576..ea517165b1 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -90,13 +90,13 @@ void ppc_translate_init(void) #endif #if !defined(TARGET_PPC64) cpu_T64[0] = tcg_global_mem_new(TCG_TYPE_I64, - TCG_AREG0, offsetof(CPUState, t0), + TCG_AREG0, offsetof(CPUState, t0_64), "T0_64"); cpu_T64[1] = tcg_global_mem_new(TCG_TYPE_I64, - TCG_AREG0, offsetof(CPUState, t1), + TCG_AREG0, offsetof(CPUState, t1_64), "T1_64"); cpu_T64[2] = tcg_global_mem_new(TCG_TYPE_I64, - TCG_AREG0, offsetof(CPUState, t2), + TCG_AREG0, offsetof(CPUState, t2_64), "T2_64"); #endif |