diff options
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/STATUS | 210 | ||||
| -rw-r--r-- | target-ppc/cpu.h | 210 | ||||
| -rw-r--r-- | target-ppc/helper.c | 12 | ||||
| -rw-r--r-- | target-ppc/translate.c | 97 | ||||
| -rw-r--r-- | target-ppc/translate_init.c | 925 |
5 files changed, 1109 insertions, 345 deletions
diff --git a/target-ppc/STATUS b/target-ppc/STATUS index 662a4a1563..190186562e 100644 --- a/target-ppc/STATUS +++ b/target-ppc/STATUS @@ -4,6 +4,216 @@ The goal of this file is to provide a reference status to avoid regressions. =============================================================================== PowerPC core emulation status +32 bits PowerPC +PowerPC 601: +INSN +SPR +MMU +EXCP + +PowerPC 602: +INSN +SPR +MMU +EXCP + +PowerPC 603: +INSN OK +SPR OK +MMU OK +EXCP OK + +PowerPC 604: +INSN OK +SPR OK +MMU OK +EXCP OK + +PowerPC 740: +INSN OK +SPR OK +MMU OK +EXCP OK + +PowerPC 745: +INSN +SPR +MMU +EXCP + +PowerPC 750: +INSN OK +SPR OK +MMU OK +EXCP OK + +PowerPC 755: +INSN +SPR +MMU +EXCP + +PowerPC 7400: +INSN KO +SPR KO +MMU OK +EXCP OK + +PowerPC 7410: +INSN KO +SPR KO +MMU OK +EXCP OK + +PowerPC 7450: +INSN KO +SPR KO +MMU OK +EXCP OK + +PowerPC 7455: +INSN KO +SPR KO +MMU OK +EXCP OK + +PowerPC 7457: +INSN KO +SPR KO +MMU OK +EXCP OK + +PowerPC 7457A: +INSN KO +SPR KO +MMU OK +EXCP OK + +64 bits PowerPC +PowerPC 970: +INSN KO +SPR KO +MMU KO +EXCP KO + +PowerPC 620: (lack of precise informations) +INSN KO +SPR KO +MMU KO +EXCP KO + +PowerPC 630: (lack of precise informations) +INSN KO +SPR KO +MMU KO +EXCP KO + +PowerPC 631: (lack of precise informations) +INSN KO +SPR KO +MMU KO +EXCP KO + +POWER4: (lack of precise informations) +INSN KO +SPR KO +MMU KO +EXCP KO + +POWER4+: (lack of precise informations) +INSN KO +SPR KO +MMU KO +EXCP KO + +POWER5: (lack of precise informations) +INSN KO +SPR KO +MMU KO +EXCP KO + +POWER5+: (lack of precise informations) +INSN KO +SPR KO +MMU KO +EXCP KO + +POWER6: (lack of precise informations) +INSN KO +SPR KO +MMU KO +EXCP KO + +RS64: (lack of precise informations) +INSN KO +SPR KO +MMU KO +EXCP KO + +RS64-II: (lack of precise informations) +INSN KO +SPR KO +MMU KO +EXCP KO + +RS64-III: (lack of precise informations) +INSN KO +SPR KO +MMU KO +EXCP KO + +RS64-IV: (lack of precise informations) +INSN KO +SPR KO +MMU KO +EXCP KO + +Embedded PowerPC cores +PowerPC 401: +INSN OK +SPR OK +MMU OK +EXCP ? + +PowerPC 403: +INSN OK +SPR OK +MMU OK +EXCP ? + +PowerPC 405: +INSN OK +SPR OK +MMU OK +EXCP OK + +PowerPC 440: +INSN OK +SPR OK +MMU ? +EXCP ? + +PowerPC 460: (lack of precise informations) +INSN KO +SPR KO +MMU KO +EXCP KO + +Freescale (to be completed) ... + +Original POWER +POWER: (lack of precise informations) +INSN KO +SPR KO +MMU KO +EXCP KO + +POWER2: (lack of precise informations) +INSN KO +SPR KO +MMU KO +EXCP KO + PowerPC CPU known to work (ie booting at least Linux 2.4): * main stream PowerPC cores - PowerPC 603 & derivatives diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index e2cf956b4a..f4c7a94678 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -94,11 +94,17 @@ enum { /* PowerPC 401 cores */ CPU_PPC_401A1 = 0x00210000, CPU_PPC_401B2 = 0x00220000, +#if 0 + CPU_PPC_401B3 = xxx, +#endif CPU_PPC_401C2 = 0x00230000, CPU_PPC_401D2 = 0x00240000, CPU_PPC_401E2 = 0x00250000, CPU_PPC_401F2 = 0x00260000, CPU_PPC_401G2 = 0x00270000, +#if 0 + CPU_PPC_401GF = xxx, +#endif #define CPU_PPC_401 CPU_PPC_401G2 CPU_PPC_IOP480 = 0x40100000, /* 401B2 ? */ CPU_PPC_COBRA = 0x10100000, /* IBM Processor for Network Resources */ @@ -107,19 +113,39 @@ enum { CPU_PPC_403GB = 0x00200100, CPU_PPC_403GC = 0x00200200, CPU_PPC_403GCX = 0x00201400, +#if 0 + CPU_PPC_403GP = xxx, +#endif #define CPU_PPC_403 CPU_PPC_403GCX /* PowerPC 405 cores */ +#if 0 + CPU_PPC_405A3 = xxx, +#endif +#if 0 + CPU_PPC_405A4 = xxx, +#endif +#if 0 + CPU_PPC_405B3 = xxx, +#endif + CPU_PPC_405D2 = 0x20010000, + CPU_PPC_405D4 = 0x41810000, CPU_PPC_405CR = 0x40110145, #define CPU_PPC_405GP CPU_PPC_405CR CPU_PPC_405EP = 0x51210950, +#if 0 + CPU_PPC_405EZ = xxx, +#endif CPU_PPC_405GPR = 0x50910951, - CPU_PPC_405D2 = 0x20010000, - CPU_PPC_405D4 = 0x41810000, +#if 0 + CPU_PPC_405LP = xxx, +#endif #define CPU_PPC_405 CPU_PPC_405D4 CPU_PPC_NPE405H = 0x414100C0, CPU_PPC_NPE405H2 = 0x41410140, CPU_PPC_NPE405L = 0x416100C0, - /* XXX: missing 405LP, LC77700 */ +#if 0 + CPU_PPC_LC77700 = xxx, +#endif /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */ #if 0 CPU_PPC_STB01000 = xxx, @@ -150,14 +176,22 @@ enum { CPU_PPC_440EP = 0x422218D3, #define CPU_PPC_440GR CPU_PPC_440EP CPU_PPC_440GP = 0x40120481, +#if 0 + CPU_PPC_440GRX = xxx, +#endif CPU_PPC_440GX = 0x51B21850, CPU_PPC_440GXc = 0x51B21892, CPU_PPC_440GXf = 0x51B21894, CPU_PPC_440SP = 0x53221850, CPU_PPC_440SP2 = 0x53221891, CPU_PPC_440SPE = 0x53421890, - /* XXX: missing 440GRX */ - /* PowerPC 460 cores - TODO */ + /* PowerPC 460 cores */ +#if 0 + CPU_PPC_464H90 = xxx, +#endif +#if 0 + CPU_PPC_464H90FP = xxx, +#endif /* PowerPC MPC 5xx cores */ CPU_PPC_5xx = 0x00020020, /* PowerPC MPC 8xx cores (aka PowerQUICC) */ @@ -197,14 +231,8 @@ enum { /* PowerPC 74x/75x cores (aka G3) */ CPU_PPC_74x = 0x00080000, CPU_PPC_740E = 0x00080100, - CPU_PPC_750E = 0x00080200, - CPU_PPC_755_10 = 0x00083100, - CPU_PPC_755_11 = 0x00083101, - CPU_PPC_755_20 = 0x00083200, - CPU_PPC_755D = 0x00083202, - CPU_PPC_755E = 0x00083203, -#define CPU_PPC_755 CPU_PPC_755E CPU_PPC_74xP = 0x10080000, + CPU_PPC_750E = 0x00080200, CPU_PPC_750CXE21 = 0x00082201, CPU_PPC_750CXE22 = 0x00082212, CPU_PPC_750CXE23 = 0x00082203, @@ -228,12 +256,20 @@ enum { CPU_PPC_750GL = 0x70020102, CPU_PPC_750L30 = 0x00088300, CPU_PPC_750L32 = 0x00088302, +#define CPU_PPC_750L CPU_PPC_750L32 CPU_PPC_750CL = 0x00087200, + CPU_PPC_755_10 = 0x00083100, + CPU_PPC_755_11 = 0x00083101, + CPU_PPC_755_20 = 0x00083200, + CPU_PPC_755D = 0x00083202, + CPU_PPC_755E = 0x00083203, +#define CPU_PPC_755 CPU_PPC_755E /* PowerPC 74xx cores (aka G4) */ CPU_PPC_7400 = 0x000C0100, CPU_PPC_7410C = 0x800C1102, CPU_PPC_7410D = 0x800C1103, CPU_PPC_7410E = 0x800C1104, +#define CPU_PPC_7410 CPU_PPC_7410E CPU_PPC_7441 = 0x80000210, CPU_PPC_7445 = 0x80010100, CPU_PPC_7447 = 0x80020100, @@ -257,6 +293,9 @@ enum { CPU_PPC_POWER4P = 0x00380000, CPU_PPC_POWER5 = 0x003A0000, CPU_PPC_POWER5P = 0x003B0000, +#if 0 + CPU_PPC_POWER6 = xxx, +#endif CPU_PPC_970 = 0x00390000, CPU_PPC_970FX10 = 0x00391100, CPU_PPC_970FX20 = 0x003C0200, @@ -399,59 +438,67 @@ enum { PPC_SPEFPU = 0x0000000200000000ULL, /* SLB management */ PPC_SLBI = 0x0000000400000000ULL, + /* PowerPC 40x ibct instructions */ + PPC_40x_ICBT = 0x0000000800000000ULL, }; /* CPU run-time flags (MMU and exception model) */ enum { - /* MMU model */ + /* MMU model */ PPC_FLAGS_MMU_MASK = 0x000000FF, - /* Standard 32 bits PowerPC MMU */ + /* Standard 32 bits PowerPC MMU */ PPC_FLAGS_MMU_32B = 0x00000000, - /* Standard 64 bits PowerPC MMU */ + /* Standard 64 bits PowerPC MMU */ PPC_FLAGS_MMU_64B = 0x00000001, - /* PowerPC 601 MMU */ + /* PowerPC 601 MMU */ PPC_FLAGS_MMU_601 = 0x00000002, /* PowerPC 6xx MMU with software TLB */ PPC_FLAGS_MMU_SOFT_6xx = 0x00000003, /* PowerPC 4xx MMU with software TLB */ PPC_FLAGS_MMU_SOFT_4xx = 0x00000004, - /* PowerPC 403 MMU */ + /* PowerPC 403 MMU */ PPC_FLAGS_MMU_403 = 0x00000005, - /* BookE FSL MMU model */ + /* BookE FSL MMU model */ PPC_FLAGS_MMU_BOOKE_FSL = 0x00000006, - /* BookE MMU model */ + /* BookE MMU model */ PPC_FLAGS_MMU_BOOKE = 0x00000007, - /* 64 bits "bridge" PowerPC MMU */ + /* 64 bits "bridge" PowerPC MMU */ PPC_FLAGS_MMU_64BRIDGE = 0x00000008, - /* Exception model */ + /* PowerPC 401 MMU (real mode only) */ + PPC_FLAGS_MMU_401 = 0x00000009, + /* Exception model */ PPC_FLAGS_EXCP_MASK = 0x0000FF00, /* Standard PowerPC exception model */ PPC_FLAGS_EXCP_STD = 0x00000000, - /* PowerPC 40x exception model */ + /* PowerPC 40x exception model */ PPC_FLAGS_EXCP_40x = 0x00000100, - /* PowerPC 601 exception model */ + /* PowerPC 601 exception model */ PPC_FLAGS_EXCP_601 = 0x00000200, - /* PowerPC 602 exception model */ + /* PowerPC 602 exception model */ PPC_FLAGS_EXCP_602 = 0x00000300, - /* PowerPC 603 exception model */ + /* PowerPC 603 exception model */ PPC_FLAGS_EXCP_603 = 0x00000400, - /* PowerPC 604 exception model */ + /* PowerPC 604 exception model */ PPC_FLAGS_EXCP_604 = 0x00000500, - /* PowerPC 7x0 exception model */ + /* PowerPC 7x0 exception model */ PPC_FLAGS_EXCP_7x0 = 0x00000600, - /* PowerPC 7x5 exception model */ + /* PowerPC 7x5 exception model */ PPC_FLAGS_EXCP_7x5 = 0x00000700, - /* PowerPC 74xx exception model */ + /* PowerPC 74xx exception model */ PPC_FLAGS_EXCP_74xx = 0x00000800, - /* PowerPC 970 exception model */ + /* PowerPC 970 exception model */ PPC_FLAGS_EXCP_970 = 0x00000900, - /* BookE exception model */ + /* BookE exception model */ PPC_FLAGS_EXCP_BOOKE = 0x00000A00, - /* Input pins model */ + /* Input pins model */ PPC_FLAGS_INPUT_MASK = 0x000F0000, + /* PowerPC 6xx bus */ PPC_FLAGS_INPUT_6xx = 0x00000000, + /* BookE bus */ PPC_FLAGS_INPUT_BookE = 0x00010000, + /* PowerPC 4xx bus */ PPC_FLAGS_INPUT_40x = 0x00020000, + /* PowerPC 970 bus */ PPC_FLAGS_INPUT_970 = 0x00030000, }; @@ -466,36 +513,40 @@ enum { #define PPC_FLAGS_TODO (0x00000000) /* PowerPC 40x instruction set */ -#define PPC_INSNS_EMB (PPC_INSNS_BASE | PPC_MEM_TLBSYNC | PPC_EMB_COMMON) +#define PPC_INSNS_EMB (PPC_INSNS_BASE | PPC_EMB_COMMON) /* PowerPC 401 */ -#define PPC_INSNS_401 (PPC_INSNS_TODO) -#define PPC_FLAGS_401 (PPC_FLAGS_TODO) +#define PPC_INSNS_401 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ + PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT) +#define PPC_FLAGS_401 (PPC_FLAGS_MMU_401 | PPC_FLAGS_EXCP_40x | \ + PPC_FLAGS_INPUT_40x) /* PowerPC 403 */ #define PPC_INSNS_403 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ - PPC_MEM_TLBIA | PPC_4xx_COMMON | PPC_40x_EXCP | \ - PPC_40x_SPEC) + PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | PPC_4xx_COMMON | \ + PPC_40x_EXCP | PPC_40x_SPEC | PPC_40x_ICBT) #define PPC_FLAGS_403 (PPC_FLAGS_MMU_403 | PPC_FLAGS_EXCP_40x | \ PPC_FLAGS_INPUT_40x) /* PowerPC 405 */ #define PPC_INSNS_405 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO | \ - PPC_CACHE_OPT | PPC_MEM_TLBIA | PPC_TB | \ - PPC_4xx_COMMON | PPC_40x_SPEC | PPC_40x_EXCP | \ - PPC_405_MAC) + PPC_CACHE_OPT | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \ + PPC_TB | PPC_4xx_COMMON | PPC_40x_SPEC | \ + PPC_40x_ICBT | PPC_40x_EXCP | PPC_405_MAC) #define PPC_FLAGS_405 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x | \ PPC_FLAGS_INPUT_40x) /* PowerPC 440 */ #define PPC_INSNS_440 (PPC_INSNS_EMB | PPC_CACHE_OPT | PPC_BOOKE | \ - PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC) + PPC_MEM_TLBSYNC | PPC_4xx_COMMON | PPC_405_MAC | \ + PPC_440_SPEC) #define PPC_FLAGS_440 (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE | \ PPC_FLAGS_INPUT_BookE) /* Generic BookE PowerPC */ -#define PPC_INSNS_BOOKE (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO | \ - PPC_FLOAT | PPC_FLOAT_OPT | PPC_CACHE_OPT) +#define PPC_INSNS_BOOKE (PPC_INSNS_EMB | PPC_MEM_TLBSYNC | PPC_BOOKE | \ + PPC_MEM_EIEIO | PPC_FLOAT | PPC_FLOAT_OPT | \ + PPC_CACHE_OPT) #define PPC_FLAGS_BOOKE (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE | \ PPC_FLAGS_INPUT_BookE) /* e500 core */ -#define PPC_INSNS_E500 (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO | \ - PPC_CACHE_OPT | PPC_E500_VECTOR) +#define PPC_INSNS_E500 (PPC_INSNS_EMB | PPC_MEM_TLBSYNC | PPC_BOOKE | \ + PPC_MEM_EIEIO | PPC_CACHE_OPT | PPC_E500_VECTOR) #define PPC_FLAGS_E500 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x | \ PPC_FLAGS_INPUT_BookE) /* Non-embedded PowerPC */ @@ -941,6 +992,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val); #define SPR_SDR1 (0x019) #define SPR_SRR0 (0x01A) #define SPR_SRR1 (0x01B) +#define SPR_AMR (0x01D) #define SPR_BOOKE_PID (0x030) #define SPR_BOOKE_DECAR (0x036) #define SPR_BOOKE_CSRR0 (0x03A) @@ -951,6 +1003,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val); #define SPR_8xx_EIE (0x050) #define SPR_8xx_EID (0x051) #define SPR_8xx_NRE (0x052) +#define SPR_CTRL (0x088) #define SPR_58x_CMPA (0x090) #define SPR_58x_CMPB (0x091) #define SPR_58x_CMPC (0x092) @@ -959,6 +1012,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val); #define SPR_58x_DER (0x094) #define SPR_58x_COUNTA (0x096) #define SPR_58x_COUNTB (0x097) +#define SPR_UCTRL (0x098) #define SPR_58x_CMPE (0x098) #define SPR_58x_CMPF (0x099) #define SPR_58x_CMPG (0x09A) @@ -992,14 +1046,18 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val); #define SPR_EAR (0x11A) #define SPR_TBL (0x11C) #define SPR_TBU (0x11D) +#define SPR_TBU40 (0x11E) #define SPR_SVR (0x11E) #define SPR_BOOKE_PIR (0x11E) #define SPR_PVR (0x11F) #define SPR_HSPRG0 (0x130) #define SPR_BOOKE_DBSR (0x130) #define SPR_HSPRG1 (0x131) +#define SPR_HDSISR (0x132) +#define SPR_HDAR (0x133) #define SPR_BOOKE_DBCR0 (0x134) #define SPR_IBCR (0x135) +#define SPR_PURR (0x135) #define SPR_BOOKE_DBCR1 (0x135) #define SPR_DBCR (0x136) #define SPR_HDEC (0x136) @@ -1039,7 +1097,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val); #define SPR_BOOKE_IVOR13 (0x19D) #define SPR_BOOKE_IVOR14 (0x19E) #define SPR_BOOKE_IVOR15 (0x19F) -#define SPR_E500_SPEFSCR (0x200) +#define SPR_BOOKE_SPEFSCR (0x200) #define SPR_E500_BBEAR (0x201) #define SPR_E500_BBTAR (0x202) #define SPR_BOOKE_ATBL (0x20E) @@ -1105,29 +1163,62 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val); #define SPR_BOOKE_TLB2CFG (0x2B2) #define SPR_BOOKE_TLB3CFG (0x2B3) #define SPR_BOOKE_EPR (0x2BE) +#define SPR_PERF0 (0x300) +#define SPR_PERF1 (0x301) +#define SPR_PERF2 (0x302) +#define SPR_PERF3 (0x303) +#define SPR_PERF4 (0x304) +#define SPR_PERF5 (0x305) +#define SPR_PERF6 (0x306) +#define SPR_PERF7 (0x307) +#define SPR_PERF8 (0x308) +#define SPR_PERF9 (0x309) +#define SPR_PERFA (0x30A) +#define SPR_PERFB (0x30B) +#define SPR_PERFC (0x30C) +#define SPR_PERFD (0x30D) +#define SPR_PERFE (0x30E) +#define SPR_PERFF (0x30F) +#define SPR_UPERF0 (0x310) +#define SPR_UPERF1 (0x311) +#define SPR_UPERF2 (0x312) +#define SPR_UPERF3 (0x313) +#define SPR_UPERF4 (0x314) +#define SPR_UPERF5 (0x315) +#define SPR_UPERF6 (0x316) +#define SPR_UPERF7 (0x317) +#define SPR_UPERF8 (0x318) +#define SPR_UPERF9 (0x319) +#define SPR_UPERFA (0x31A) +#define SPR_UPERFB (0x31B) +#define SPR_UPERFC (0x31C) +#define SPR_UPERFD (0x31D) +#define SPR_UPERFE (0x31E) +#define SPR_UPERFF (0x31F) #define SPR_440_INV0 (0x370) #define SPR_440_INV1 (0x371) #define SPR_440_INV2 (0x372) #define SPR_440_INV3 (0x373) -#define SPR_440_IVT0 (0x374) -#define SPR_440_IVT1 (0x375) -#define SPR_440_IVT2 (0x376) -#define SPR_440_IVT3 (0x377) +#define SPR_440_ITV0 (0x374) +#define SPR_440_ITV1 (0x375) +#define SPR_440_ITV2 (0x376) +#define SPR_440_ITV3 (0x377) +#define SPR_PPR (0x380) #define SPR_440_DNV0 (0x390) #define SPR_440_DNV1 (0x391) #define SPR_440_DNV2 (0x392) #define SPR_440_DNV3 (0x393) -#define SPR_440_DVT0 (0x394) -#define SPR_440_DVT1 (0x395) -#define SPR_440_DVT2 (0x396) -#define SPR_440_DVT3 (0x397) +#define SPR_440_DTV0 (0x394) +#define SPR_440_DTV1 (0x395) +#define SPR_440_DTV2 (0x396) +#define SPR_440_DTV3 (0x397) #define SPR_440_DVLIM (0x398) #define SPR_440_IVLIM (0x399) #define SPR_440_RSTCFG (0x39B) -#define SPR_BOOKE_DCBTRL (0x39C) -#define SPR_BOOKE_DCBTRH (0x39D) -#define SPR_BOOKE_ICBTRL (0x39E) -#define SPR_BOOKE_ICBTRH (0x39F) +#define SPR_BOOKE_DCDBTRL (0x39C) +#define SPR_BOOKE_DCDBTRH (0x39D) +#define SPR_BOOKE_ICDBTRL (0x39E) +#define SPR_BOOKE_ICDBTRH (0x39F) #define SPR_UMMCR0 (0x3A8) #define SPR_UPMC1 (0x3A9) #define SPR_UPMC2 (0x3AA) @@ -1166,7 +1257,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val); #define SPR_DCMP (0x3D1) #define SPR_HASH1 (0x3D2) #define SPR_HASH2 (0x3D3) -#define SPR_BOOKE_ICBDR (0x3D3) +#define SPR_BOOKE_ICDBDR (0x3D3) #define SPR_IMISS (0x3D4) #define SPR_40x_ESR (0x3D4) #define SPR_ICMP (0x3D5) @@ -1204,6 +1295,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val); #define SPR_40x_IAC2 (0x3F5) #define SPR_601_HID5 (0x3F5) #define SPR_40x_DAC1 (0x3F6) +#define SPR_DABRX (0x3F7) #define SPR_40x_DAC2 (0x3F7) #define SPR_BOOKE_MMUCFG (0x3F7) #define SPR_L2PM (0x3F8) diff --git a/target-ppc/helper.c b/target-ppc/helper.c index 534ad6b5d3..e5d152d7e6 100644 --- a/target-ppc/helper.c +++ b/target-ppc/helper.c @@ -1072,6 +1072,7 @@ static int check_physical (CPUState *env, mmu_ctx_t *ctx, case PPC_FLAGS_MMU_SOFT_6xx: case PPC_FLAGS_MMU_601: case PPC_FLAGS_MMU_SOFT_4xx: + case PPC_FLAGS_MMU_401: ctx->prot |= PAGE_WRITE; break; #if defined(TARGET_PPC64) @@ -1168,6 +1169,9 @@ int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr, /* XXX: TODO */ cpu_abort(env, "BookE FSL MMU model not implemented\n"); return -1; + case PPC_FLAGS_MMU_401: + cpu_abort(env, "PowerPC 401 does not do any translation\n"); + return -1; default: cpu_abort(env, "Unknown or invalid MMU model\n"); return -1; @@ -1267,6 +1271,10 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, /* XXX: TODO */ cpu_abort(env, "MMU model not implemented\n"); return -1; + case PPC_FLAGS_MMU_401: + cpu_abort(env, "PowerPC 401 should never raise any MMU " + "exceptions\n"); + return -1; default: cpu_abort(env, "Unknown or invalid MMU model\n"); return -1; @@ -1348,6 +1356,10 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, /* XXX: TODO */ cpu_abort(env, "MMU model not implemented\n"); return -1; + case PPC_FLAGS_MMU_401: + cpu_abort(env, "PowerPC 401 should never raise any MMU " + "exceptions\n"); + return -1; default: cpu_abort(env, "Unknown or invalid MMU model\n"); return -1; diff --git a/target-ppc/translate.c b/target-ppc/translate.c index db90f3f4db..9d6bf32066 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -4221,12 +4221,14 @@ GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2) } /* BookE specific instructions */ +/* XXX: not implemented on 440 ? */ GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_BOOKE) { /* XXX: TODO */ RET_INVAL(ctx); } +/* XXX: not implemented on 440 ? */ GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_BOOKE) { #if defined(CONFIG_USER_ONLY) @@ -4329,98 +4331,99 @@ static inline void gen_405_mulladd_insn (DisasContext *ctx, int opc2, int opc3, } } -#define GEN_MAC_HANDLER(name, opc2, opc3) \ -GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \ +#define GEN_MAC_HANDLER(name, opc2, opc3, is_440) \ +GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, \ + is_440 ? PPC_440_SPEC : PPC_405_MAC) \ { \ gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ rD(ctx->opcode), Rc(ctx->opcode)); \ } /* macchw - macchw. */ -GEN_MAC_HANDLER(macchw, 0x0C, 0x05); +GEN_MAC_HANDLER(macchw, 0x0C, 0x05, 0); /* macchwo - macchwo. */ -GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); +GEN_MAC_HANDLER(macchwo, 0x0C, 0x15, 0); /* macchws - macchws. */ -GEN_MAC_HANDLER(macchws, 0x0C, 0x07); +GEN_MAC_HANDLER(macchws, 0x0C, 0x07, 0); /* macchwso - macchwso. */ -GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); +GEN_MAC_HANDLER(macchwso, 0x0C, 0x17, 0); /* macchwsu - macchwsu. */ -GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); +GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06, 0); /* macchwsuo - macchwsuo. */ -GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); +GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16, 0); /* macchwu - macchwu. */ -GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); +GEN_MAC_HANDLER(macchwu, 0x0C, 0x04, 0); /* macchwuo - macchwuo. */ -GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); +GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14, 0); /* machhw - machhw. */ -GEN_MAC_HANDLER(machhw, 0x0C, 0x01); +GEN_MAC_HANDLER(machhw, 0x0C, 0x01, 0); /* machhwo - machhwo. */ -GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); +GEN_MAC_HANDLER(machhwo, 0x0C, 0x11, 0); /* machhws - machhws. */ -GEN_MAC_HANDLER(machhws, 0x0C, 0x03); +GEN_MAC_HANDLER(machhws, 0x0C, 0x03, 0); /* machhwso - machhwso. */ -GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); +GEN_MAC_HANDLER(machhwso, 0x0C, 0x13, 0); /* machhwsu - machhwsu. */ -GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); +GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02, 0); /* machhwsuo - machhwsuo. */ -GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); +GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12, 0); /* machhwu - machhwu. */ -GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); +GEN_MAC_HANDLER(machhwu, 0x0C, 0x00, 0); /* machhwuo - machhwuo. */ -GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); +GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10, 0); /* maclhw - maclhw. */ -GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); +GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D, 0); /* maclhwo - maclhwo. */ -GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); +GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D, 0); /* maclhws - maclhws. */ -GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); +GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F, 0); /* maclhwso - maclhwso. */ -GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); +GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F, 0); /* maclhwu - maclhwu. */ -GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); +GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C, 0); /* maclhwuo - maclhwuo. */ -GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); +GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C, 0); /* maclhwsu - maclhwsu. */ -GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); +GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E, 0); /* maclhwsuo - maclhwsuo. */ -GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); +GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E, 0); /* nmacchw - nmacchw. */ -GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); +GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05, 0); /* nmacchwo - nmacchwo. */ -GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); +GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15, 0); /* nmacchws - nmacchws. */ -GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); +GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07, 0); /* nmacchwso - nmacchwso. */ -GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); +GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17, 0); /* nmachhw - nmachhw. */ -GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); +GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01, 0); /* nmachhwo - nmachhwo. */ -GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); +GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11, 0); /* nmachhws - nmachhws. */ -GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); +GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03, 1); /* nmachhwso - nmachhwso. */ -GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); +GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13, 1); /* nmaclhw - nmaclhw. */ -GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); +GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D, 1); /* nmaclhwo - nmaclhwo. */ -GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); +GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D, 1); /* nmaclhws - nmaclhws. */ -GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); +GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F, 1); /* nmaclhwso - nmaclhwso. */ -GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); +GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F, 1); /* mulchw - mulchw. */ -GEN_MAC_HANDLER(mulchw, 0x08, 0x05); +GEN_MAC_HANDLER(mulchw, 0x08, 0x05, 0); /* mulchwu - mulchwu. */ -GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); +GEN_MAC_HANDLER(mulchwu, 0x08, 0x04, 0); /* mulhhw - mulhhw. */ -GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); +GEN_MAC_HANDLER(mulhhw, 0x08, 0x01, 0); /* mulhhwu - mulhhwu. */ -GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); +GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00, 0); /* mullhw - mullhw. */ -GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); +GEN_MAC_HANDLER(mullhw, 0x08, 0x0D, 0); /* mullhwu - mullhwu. */ -GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); +GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C, 0); /* mfdcr */ GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_EMB_COMMON) @@ -4459,6 +4462,7 @@ GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_EMB_COMMON) } /* mfdcrx */ +/* XXX: not implemented on 440 ? */ GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000001, PPC_BOOKE) { #if defined(CONFIG_USER_ONLY) @@ -4475,6 +4479,7 @@ GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000001, PPC_BOOKE) } /* mtdcrx */ +/* XXX: not implemented on 440 ? */ GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000001, PPC_BOOKE) { #if defined(CONFIG_USER_ONLY) @@ -4521,7 +4526,7 @@ GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON) } /* icbt */ -GEN_HANDLER(icbt_40x, 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_SPEC) +GEN_HANDLER(icbt_40x, 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT) { /* interpreted as no-op */ /* XXX: specification say this is treated as a load by the MMU @@ -4589,6 +4594,7 @@ GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE) } /* BookE specific */ +/* XXX: not implemented on 440 ? */ GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_BOOKE) { #if defined(CONFIG_USER_ONLY) @@ -4604,6 +4610,7 @@ GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_BOOKE) #endif } +/* XXX: not implemented on 440 ? */ GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_BOOKE) { #if defined(CONFIG_USER_ONLY) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 131346d815..82270e659e 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -1123,6 +1123,7 @@ static void gen_spr_BookE (CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); +#if 0 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, @@ -1139,6 +1140,7 @@ static void gen_spr_BookE (CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); +#endif /* Debug */ /* XXX : not implemented */ spr_register(env, SPR_BOOKE_IAC1, "IAC1", @@ -1277,6 +1279,7 @@ static void gen_spr_BookE (CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); +#if 0 spr_register(env, SPR_BOOKE_IVOR32, "IVOR32", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, @@ -1301,6 +1304,7 @@ static void gen_spr_BookE (CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); +#endif spr_register(env, SPR_BOOKE_PID, "PID", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, @@ -1469,22 +1473,22 @@ static void gen_spr_440 (CPUPPCState *env) &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ - spr_register(env, SPR_440_DVT0, "DVT0", + spr_register(env, SPR_440_DTV0, "DTV0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ - spr_register(env, SPR_440_DVT1, "DVT1", + spr_register(env, SPR_440_DTV1, "DTV1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ - spr_register(env, SPR_440_DVT2, "DVT2", + spr_register(env, SPR_440_DTV2, "DTV2", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ - spr_register(env, SPR_440_DVT3, "DVT3", + spr_register(env, SPR_440_DTV3, "DTV3", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); @@ -1514,22 +1518,22 @@ static void gen_spr_440 (CPUPPCState *env) &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ - spr_register(env, SPR_440_IVT0, "IVT0", + spr_register(env, SPR_440_ITV0, "ITV0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ - spr_register(env, SPR_440_IVT1, "IVT1", + spr_register(env, SPR_440_ITV1, "ITV1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ - spr_register(env, SPR_440_IVT2, "IVT2", + spr_register(env, SPR_440_ITV2, "ITV2", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ - spr_register(env, SPR_440_IVT3, "IVT3", + spr_register(env, SPR_440_ITV3, "ITV3", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); @@ -1540,27 +1544,27 @@ static void gen_spr_440 (CPUPPCState *env) 0x00000000); /* Cache debug */ /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_DCBTRH, "DCBTRH", + spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, SPR_NOACCESS, 0x00000000); /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_DCBTRL, "DCBTRL", + spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, SPR_NOACCESS, 0x00000000); /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_ICBDR, "ICBDR", + spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, SPR_NOACCESS, 0x00000000); /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_ICBTRH, "ICBTRH", + spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, SPR_NOACCESS, 0x00000000); /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_ICBTRL, "ICBTRL", + spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, SPR_NOACCESS, 0x00000000); @@ -1605,7 +1609,7 @@ static void gen_spr_40x (CPUPPCState *env) &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ - spr_register(env, SPR_BOOKE_ICBDR, "ICBDR", + spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, SPR_NOACCESS, 0x00000000); @@ -1614,15 +1618,6 @@ static void gen_spr_40x (CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0xFFFFFFFF); - spr_register(env, SPR_40x_ZPR, "ZPR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* MMU */ - spr_register(env, SPR_40x_PID, "PID", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); /* Exception */ spr_register(env, SPR_40x_DEAR, "DEAR", SPR_NOACCESS, SPR_NOACCESS, @@ -1657,58 +1652,62 @@ static void gen_spr_40x (CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_booke_tsr, 0x00000000); - /* Debug interface */ - /* XXX : not implemented */ - spr_register(env, SPR_40x_DAC1, "DAC1", +} + +/* SPR specific to PowerPC 405 implementation */ +static void gen_spr_405 (CPUPPCState *env) +{ + /* MMU */ + spr_register(env, SPR_40x_PID, "PID", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); - spr_register(env, SPR_40x_DAC2, "DAC2", + spr_register(env, SPR_4xx_CCR0, "CCR0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, - 0x00000000); + 0x00700000); + /* Debug interface */ /* XXX : not implemented */ spr_register(env, SPR_40x_DBCR0, "DBCR0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_40x_dbcr0, 0x00000000); /* XXX : not implemented */ + spr_register(env, SPR_405_DBCR1, "DBCR1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ spr_register(env, SPR_40x_DBSR, "DBSR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_clear, /* Last reset was system reset */ 0x00000300); /* XXX : not implemented */ - spr_register(env, SPR_40x_IAC1, "IAC1", + spr_register(env, SPR_40x_DAC1, "DAC1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); - spr_register(env, SPR_40x_IAC2, "IAC2", + spr_register(env, SPR_40x_DAC2, "DAC2", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); -} - -/* SPR specific to PowerPC 405 implementation */ -static void gen_spr_405 (CPUPPCState *env) -{ - spr_register(env, SPR_4xx_CCR0, "CCR0", + /* XXX : not implemented */ + spr_register(env, SPR_405_DVC1, "DVC1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, - 0x00700000); - /* Debug */ + 0x00000000); /* XXX : not implemented */ - spr_register(env, SPR_405_DBCR1, "DBCR1", + spr_register(env, SPR_405_DVC2, "DVC2", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); /* XXX : not implemented */ - spr_register(env, SPR_405_DVC1, "DVC1", + spr_register(env, SPR_40x_IAC1, "IAC1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_405_DVC2, "DVC2", + spr_register(env, SPR_40x_IAC2, "IAC2", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); @@ -1727,6 +1726,10 @@ static void gen_spr_405 (CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_40x_sler, 0x00000000); + spr_register(env, SPR_40x_ZPR, "ZPR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_405_SU0R, "SU0R", SPR_NOACCESS, SPR_NOACCESS, @@ -1799,10 +1802,76 @@ static void gen_spr_401_403 (CPUPPCState *env) 0x00000000); } +/* SPR specific to PowerPC 401 implementation */ +static void gen_spr_401 (CPUPPCState *env) +{ + /* Debug interface */ + /* XXX : not implemented */ + spr_register(env, SPR_40x_DBCR0, "DBCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_40x_dbcr0, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_40x_DBSR, "DBSR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_clear, + /* Last reset was system reset */ + 0x00000300); + /* XXX : not implemented */ + spr_register(env, SPR_40x_DAC1, "DAC", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_40x_IAC1, "IAC", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Storage control */ + spr_register(env, SPR_405_SLER, "SLER", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_40x_sler, + 0x00000000); +} + /* SPR specific to PowerPC 403 implementation */ static void gen_spr_403 (CPUPPCState *env) { + /* Debug interface */ + /* XXX : not implemented */ + spr_register(env, SPR_40x_DBCR0, "DBCR0", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_40x_dbcr0, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_40x_DBSR, "DBSR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_clear, + /* Last reset was system reset */ + 0x00000300); + /* XXX : not implemented */ + spr_register(env, SPR_40x_DAC1, "DAC1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_40x_DAC2, "DAC2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* XXX : not implemented */ + spr_register(env, SPR_40x_IAC1, "IAC1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_40x_IAC2, "IAC2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); /* MMU */ + spr_register(env, SPR_40x_PID, "PID", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); spr_register(env, SPR_403_PBL1, "PBL1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_403_pbr, &spr_write_403_pbr, @@ -1819,14 +1888,7 @@ static void gen_spr_403 (CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_403_pbr, &spr_write_403_pbr, 0x00000000); - /* Debug */ - /* XXX : not implemented */ - spr_register(env, SPR_40x_DAC2, "DAC2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_40x_IAC2, "IAC2", + spr_register(env, SPR_40x_ZPR, "ZPR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); @@ -1843,23 +1905,40 @@ static void gen_spr_compress (CPUPPCState *env) } #endif -// XXX: TODO (64 bits PowerPC SPRs) +// XXX: TODO /* - * ASR => SPR 280 (64 bits) - * FPECR => SPR 1022 (?) - * VRSAVE => SPR 256 (Altivec) - * SCOMC => SPR 276 (64 bits ?) - * SCOMD => SPR 277 (64 bits ?) - * HSPRG0 => SPR 304 (hypervisor) - * HSPRG1 => SPR 305 (hypervisor) - * HDEC => SPR 310 (hypervisor) - * HIOR => SPR 311 (hypervisor) - * RMOR => SPR 312 (970) - * HRMOR => SPR 313 (hypervisor) - * HSRR0 => SPR 314 (hypervisor) - * HSRR1 => SPR 315 (hypervisor) - * LPCR => SPR 316 (970) - * LPIDR => SPR 317 (970) + * AMR => SPR 29 (Power 2.04) + * CTRL => SPR 136 (Power 2.04) + * CTRL => SPR 152 (Power 2.04) + * VRSAVE => SPR 256 (Altivec) + * SCOMC => SPR 276 (64 bits ?) + * SCOMD => SPR 277 (64 bits ?) + * ASR => SPR 280 (64 bits) + * TBU40 => SPR 286 (Power 2.04 hypv) + * HSPRG0 => SPR 304 (Power 2.04 hypv) + * HSPRG1 => SPR 305 (Power 2.04 hypv) + * HDSISR => SPR 306 (Power 2.04 hypv) + * HDAR => SPR 307 (Power 2.04 hypv) + * PURR => SPR 309 (Power 2.04 hypv) + * HDEC => SPR 310 (Power 2.04 hypv) + * HIOR => SPR 311 (hypv) + * RMOR => SPR 312 (970) + * HRMOR => SPR 313 (Power 2.04 hypv) + * HSRR0 => SPR 314 (Power 2.04 hypv) + * HSRR1 => SPR 315 (Power 2.04 hypv) + * LPCR => SPR 316 (970) + * LPIDR => SPR 317 (970) + * SPEFSCR => SPR 512 (Power 2.04 emb) + * ATBL => SPR 526 (Power 2.04 emb) + * ATBU => SPR 527 (Power 2.04 emb) + * EPR => SPR 702 (Power 2.04 emb) + * perf => 768-783 (Power 2.04) + * perf => 784-799 (Power 2.04) + * PPR => SPR 896 (Power 2.04) + * EPLC => SPR 947 (Power 2.04 emb) + * EPSC => SPR 948 (Power 2.04 emb) + * DABRX => 1015 (Power 2.04 hypv) + * FPECR => SPR 1022 (?) * ... and more (thermal management, performance counters, ...) */ @@ -1886,6 +1965,9 @@ static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def) /* Embedded PowerPC from IBM */ case CPU_PPC_401A1: /* 401 A1 family */ case CPU_PPC_401B2: /* 401 B2 family */ +#if 0 + case CPU_PPC_401B3: /* 401 B3 family */ +#endif case CPU_PPC_401C2: /* 401 C2 family */ case CPU_PPC_401D2: /* 401 D2 family */ case CPU_PPC_401E2: /* 401 E2 family */ @@ -1896,6 +1978,7 @@ static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def) gen_spr_generic(env); gen_spr_40x(env); gen_spr_401_403(env); + gen_spr_401(env); #if defined (TODO) /* XXX: optional ? */ gen_spr_compress(env); @@ -2413,7 +2496,7 @@ static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def) #endif /* defined (TARGET_PPC64) */ #if defined (TODO) - /* POWER */ + /* POWER */ case CPU_POWER: /* POWER */ case CPU_POWER2: /* POWER2 */ break; @@ -2460,7 +2543,7 @@ static void dump_sprs (CPUPPCState *env) uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS; ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS; if (sw || sr || uw || ur) { - printf("%4d (%03x) %8s s%c%c u%c%c\n", + printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n", (i << 5) | j, (i << 5) | j, spr->name, sw ? 'w' : '-', sr ? 'r' : '-', uw ? 'w' : '-', ur ? 'r' : '-'); @@ -2678,15 +2761,15 @@ static int create_ppc_opcodes (CPUPPCState *env, ppc_def_t *def) if (opc1 != 0x00) { if (opc->opc3 == 0xFF) { if (opc->opc2 == 0xFF) { - printf(" %02x -- -- (%2d ----) : %s\n", + printf("INSN: %02x -- -- (%02d ----) : %s\n", opc->opc1, opc->opc1, opc->oname); } else { - printf(" %02x %02x -- (%2d %4d) : %s\n", + printf("INSN: %02x %02x -- (%02d %04d) : %s\n", opc->opc1, opc->opc2, opc->opc1, opc->opc2, opc->oname); } } else { - printf(" %02x %02x %02x (%2d %4d) : %s\n", + printf("INSN: %02x %02x %02x (%02d %04d) : %s\n", opc->opc1, opc->opc2, opc->opc3, opc->opc1, (opc->opc3 << 5) | opc->opc2, opc->oname); @@ -2724,15 +2807,98 @@ int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def) /* PowerPC CPU definitions */ static ppc_def_t ppc_defs[] = { /* Embedded PowerPC */ -#if defined (TODO) - /* PowerPC 401 */ + /* Generic PowerPC 401 */ { .name = "401", .pvr = CPU_PPC_401, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_401, .flags = PPC_FLAGS_401, - .msr_mask = xxx, + .msr_mask = 0x000FD201, + }, + /* PowerPC 401A1 */ + { + .name = "401a1", + .pvr = CPU_PPC_401A1, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_401, + .flags = PPC_FLAGS_401, + .msr_mask = 0x000FD201, + }, + /* PowerPC 401B2 */ + { + .name = "401b2", + .pvr = CPU_PPC_401B2, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_401, + .flags = PPC_FLAGS_401, + .msr_mask = 0x000FD201, + }, +#if defined (TODO) + /* PowerPC 401B3 */ + { + .name = "401b3", + .pvr = CPU_PPC_401B3, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_401, + .flags = PPC_FLAGS_401, + .msr_mask = 0x000FD201, + }, +#endif + /* PowerPC 401C2 */ + { + .name = "401c2", + .pvr = CPU_PPC_401C2, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_401, + .flags = PPC_FLAGS_401, + .msr_mask = 0x000FD201, + }, + /* PowerPC 401D2 */ + { + .name = "401d2", + .pvr = CPU_PPC_401D2, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_401, + .flags = PPC_FLAGS_401, + .msr_mask = 0x000FD201, + }, + /* PowerPC 401E2 */ + { + .name = "401e2", + .pvr = CPU_PPC_401E2, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_401, + .flags = PPC_FLAGS_401, + .msr_mask = 0x000FD201, + }, + /* PowerPC 401F2 */ + { + .name = "401f2", + .pvr = CPU_PPC_401F2, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_401, + .flags = PPC_FLAGS_401, + .msr_mask = 0x000FD201, + }, + /* PowerPC 401G2 */ + { + .name = "401g2", + .pvr = CPU_PPC_401G2, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_401, + .flags = PPC_FLAGS_401, + .msr_mask = 0x000FD201, + }, +#if defined (TODO) + /* PowerPC 401G2 */ + { + .name = "401gf", + .pvr = CPU_PPC_401GF, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_401, + .flags = PPC_FLAGS_401, + .msr_mask = 0x000FD201, }, #endif #if defined (TODO) @@ -2740,10 +2906,10 @@ static ppc_def_t ppc_defs[] = { { .name = "iop480", .pvr = CPU_PPC_IOP480, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_401, .flags = PPC_FLAGS_401, - .msr_mask = xxx, + .msr_mask = 0x000FD201, }, #endif #if defined (TODO) @@ -2751,62 +2917,63 @@ static ppc_def_t ppc_defs[] = { { .name = "Cobra", .pvr = CPU_PPC_COBRA, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_401, .flags = PPC_FLAGS_401, - .msr_mask = xxx, + .msr_mask = 0x000FD201, }, #endif -#if defined (TODO) /* Generic PowerPC 403 */ { .name = "403", .pvr = CPU_PPC_403, - .pvr_mask = 0xFFFFFF00, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_403, .flags = PPC_FLAGS_403, .msr_mask = 0x000000000007D23DULL, }, -#endif -#if defined (TODO) /* PowerPC 403 GA */ { .name = "403ga", .pvr = CPU_PPC_403GA, - .pvr_mask = 0xFFFFFF00, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_403, .flags = PPC_FLAGS_403, .msr_mask = 0x000000000007D23DULL, }, -#endif -#if defined (TODO) /* PowerPC 403 GB */ { .name = "403gb", .pvr = CPU_PPC_403GB, - .pvr_mask = 0xFFFFFF00, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_403, .flags = PPC_FLAGS_403, .msr_mask = 0x000000000007D23DULL, }, -#endif -#if defined (TODO) /* PowerPC 403 GC */ { .name = "403gc", .pvr = CPU_PPC_403GC, - .pvr_mask = 0xFFFFFF00, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_403, .flags = PPC_FLAGS_403, .msr_mask = 0x000000000007D23DULL, }, -#endif -#if defined (TODO) /* PowerPC 403 GCX */ { .name = "403gcx", .pvr = CPU_PPC_403GCX, - .pvr_mask = 0xFFFFFF00, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_403, + .flags = PPC_FLAGS_403, + .msr_mask = 0x000000000007D23DULL, + }, +#if defined (TODO) + /* PowerPC 403 GP */ + { + .name = "403gp", + .pvr = CPU_PPC_403GP, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_403, .flags = PPC_FLAGS_403, .msr_mask = 0x000000000007D23DULL, @@ -2816,7 +2983,58 @@ static ppc_def_t ppc_defs[] = { { .name = "405", .pvr = CPU_PPC_405, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_405, + .flags = PPC_FLAGS_405, + .msr_mask = 0x00000000020EFF30ULL, + }, +#if defined (TODO) + /* PowerPC 405 A3 */ + { + .name = "405a3", + .pvr = CPU_PPC_405A3, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_405, + .flags = PPC_FLAGS_405, + .msr_mask = 0x00000000020EFF30ULL, + }, +#endif +#if defined (TODO) + /* PowerPC 405 A4 */ + { + .name = "405a4", + .pvr = CPU_PPC_405A4, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_405, + .flags = PPC_FLAGS_405, + .msr_mask = 0x00000000020EFF30ULL, + }, +#endif +#if defined (TODO) + /* PowerPC 405 B3 */ + { + .name = "405b3", + .pvr = CPU_PPC_405B3, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_405, + .flags = PPC_FLAGS_405, + .msr_mask = 0x00000000020EFF30ULL, + }, +#endif + /* PowerPC 405 D2 */ + { + .name = "405d2", + .pvr = CPU_PPC_405D2, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_405, + .flags = PPC_FLAGS_405, + .msr_mask = 0x00000000020EFF30ULL, + }, + /* PowerPC 405 D4 */ + { + .name = "405d4", + .pvr = CPU_PPC_405D4, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_405, .flags = PPC_FLAGS_405, .msr_mask = 0x00000000020EFF30ULL, @@ -2824,23 +3042,21 @@ static ppc_def_t ppc_defs[] = { /* PowerPC 405 CR */ { .name = "405cr", - .pvr = CPU_PPC_405, + .pvr = CPU_PPC_405CR, .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_405, .flags = PPC_FLAGS_405, .msr_mask = 0x00000000020EFF30ULL, }, -#if defined (TODO) /* PowerPC 405 GP */ { .name = "405gp", - .pvr = CPU_PPC_405, + .pvr = CPU_PPC_405GP, .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_405, .flags = PPC_FLAGS_405, .msr_mask = 0x00000000020EFF30ULL, }, -#endif /* PowerPC 405 EP */ { .name = "405ep", @@ -2872,36 +3088,35 @@ static ppc_def_t ppc_defs[] = { .msr_mask = 0x00000000020EFF30ULL, }, #endif - /* PowerPC 405 D2 */ +#if defined (TODO) + /* PowerPC 405 LP */ { - .name = "405d2", - .pvr = CPU_PPC_405D2, + .name = "405lp", + .pvr = CPU_PPC_405EZ, .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_405, .flags = PPC_FLAGS_405, .msr_mask = 0x00000000020EFF30ULL, }, - /* PowerPC 405 D4 */ +#endif + /* Npe405 H */ { - .name = "405d4", - .pvr = CPU_PPC_405D4, + .name = "Npe405H", + .pvr = CPU_PPC_NPE405H, .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_405, .flags = PPC_FLAGS_405, .msr_mask = 0x00000000020EFF30ULL, }, -#if defined (TODO) - /* Npe405 H */ + /* Npe405 H2 */ { - .name = "Npe405H", - .pvr = CPU_PPC_NPE405H, + .name = "Npe405H2", + .pvr = CPU_PPC_NPE405H2, .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_405, .flags = PPC_FLAGS_405, .msr_mask = 0x00000000020EFF30ULL, }, -#endif -#if defined (TODO) /* Npe405 L */ { .name = "Npe405L", @@ -2911,6 +3126,16 @@ static ppc_def_t ppc_defs[] = { .flags = PPC_FLAGS_405, .msr_mask = 0x00000000020EFF30ULL, }, +#if defined (TODO) + /* PowerPC LP777000 */ + { + .name = "lp777000", + .pvr = CPU_PPC_LP777000, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_405, + .flags = PPC_FLAGS_405, + .msr_mask = 0x00000000020EFF30ULL, + }, #endif #if defined (TODO) /* STB010000 */ @@ -2978,7 +3203,7 @@ static ppc_def_t ppc_defs[] = { .msr_mask = 0x00000000020EFF30ULL, }, #endif -#if defined (TODO) +#if defined (TODO) || 1 /* STB25xx */ { .name = "STB25", @@ -3035,105 +3260,98 @@ static ppc_def_t ppc_defs[] = { .msr_mask = 0x00000000020EFF30ULL, }, #endif -#if defined (TODO) /* PowerPC 440 EP */ { .name = "440ep", .pvr = CPU_PPC_440EP, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_440, .flags = PPC_FLAGS_440, .msr_mask = 0x000000000006D630ULL, }, -#endif -#if defined (TODO) /* PowerPC 440 GR */ { .name = "440gr", .pvr = CPU_PPC_440GR, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_440, .flags = PPC_FLAGS_440, .msr_mask = 0x000000000006D630ULL, }, -#endif -#if defined (TODO) /* PowerPC 440 GP */ { .name = "440gp", .pvr = CPU_PPC_440GP, - .pvr_mask = 0xFFFFFF00, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_440, .flags = PPC_FLAGS_440, .msr_mask = 0x000000000006D630ULL, }, -#endif #if defined (TODO) + /* PowerPC 440 GRX */ + { + .name = "440grx", + .pvr = CPU_PPC_440GRX, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_440, + .flags = PPC_FLAGS_440, + .msr_mask = 0x000000000006D630ULL, + }, +#endif /* PowerPC 440 GX */ { .name = "440gx", .pvr = CPU_PPC_440GX, - .pvr_mask = 0xFFFF0000, - .insns_flags = PPC_INSNS_405, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_440, .flags = PPC_FLAGS_440, .msr_mask = 0x000000000006D630ULL, }, -#endif -#if defined (TODO) /* PowerPC 440 GXc */ { .name = "440gxc", - .pvr = CPU_PPC_440GXC, - .pvr_mask = 0xFFFF0000, - .insns_flags = PPC_INSNS_405, + .pvr = CPU_PPC_440GXc, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_440, .flags = PPC_FLAGS_440, .msr_mask = 0x000000000006D630ULL, }, -#endif -#if defined (TODO) /* PowerPC 440 GXf */ { .name = "440gxf", - .pvr = CPU_PPC_440GXF, - .pvr_mask = 0xFFFF0000, - .insns_flags = PPC_INSNS_405, + .pvr = CPU_PPC_440GXf, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_440, .flags = PPC_FLAGS_440, .msr_mask = 0x000000000006D630ULL, }, -#endif -#if defined (TODO) /* PowerPC 440 SP */ { .name = "440sp", .pvr = CPU_PPC_440SP, - .pvr_mask = 0xFFFF0000, - .insns_flags = PPC_INSNS_405, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_440, .flags = PPC_FLAGS_440, .msr_mask = 0x000000000006D630ULL, }, -#endif -#if defined (TODO) /* PowerPC 440 SP2 */ { .name = "440sp2", .pvr = CPU_PPC_440SP2, - .pvr_mask = 0xFFFF0000, - .insns_flags = PPC_INSNS_405, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_440, .flags = PPC_FLAGS_440, .msr_mask = 0x000000000006D630ULL, }, -#endif -#if defined (TODO) /* PowerPC 440 SPE */ { .name = "440spe", .pvr = CPU_PPC_440SPE, - .pvr_mask = 0xFFFF0000, - .insns_flags = PPC_INSNS_405, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_440, .flags = PPC_FLAGS_440, .msr_mask = 0x000000000006D630ULL, }, -#endif /* Fake generic BookE PowerPC */ { .name = "BookE", @@ -3157,7 +3375,7 @@ static ppc_def_t ppc_defs[] = { { .name = "601", .pvr = CPU_PPC_601, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_601, .flags = PPC_FLAGS_601, .msr_mask = 0x000000000000FD70ULL, @@ -3168,7 +3386,7 @@ static ppc_def_t ppc_defs[] = { { .name = "602", .pvr = CPU_PPC_602, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_602, .flags = PPC_FLAGS_602, .msr_mask = 0x0000000000C7FF73ULL, @@ -3258,7 +3476,7 @@ static ppc_def_t ppc_defs[] = { { .name = "G2", .pvr = CPU_PPC_G2, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_G2, .flags = PPC_FLAGS_G2, .msr_mask = 0x000000000006FFF2ULL, @@ -3266,7 +3484,7 @@ static ppc_def_t ppc_defs[] = { { .name = "G2h4", .pvr = CPU_PPC_G2H4, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_G2, .flags = PPC_FLAGS_G2, .msr_mask = 0x000000000006FFF2ULL, @@ -3274,7 +3492,7 @@ static ppc_def_t ppc_defs[] = { { .name = "G2gp", .pvr = CPU_PPC_G2gp, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_G2, .flags = PPC_FLAGS_G2, .msr_mask = 0x000000000006FFF2ULL, @@ -3282,7 +3500,7 @@ static ppc_def_t ppc_defs[] = { { .name = "G2ls", .pvr = CPU_PPC_G2ls, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_G2, .flags = PPC_FLAGS_G2, .msr_mask = 0x000000000006FFF2ULL, @@ -3290,7 +3508,7 @@ static ppc_def_t ppc_defs[] = { { /* Same as G2, with LE mode support */ .name = "G2le", .pvr = CPU_PPC_G2LE, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_G2, .flags = PPC_FLAGS_G2, .msr_mask = 0x000000000007FFF3ULL, @@ -3298,7 +3516,7 @@ static ppc_def_t ppc_defs[] = { { .name = "G2legp", .pvr = CPU_PPC_G2LEgp, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_G2, .flags = PPC_FLAGS_G2, .msr_mask = 0x000000000007FFF3ULL, @@ -3306,7 +3524,7 @@ static ppc_def_t ppc_defs[] = { { .name = "G2lels", .pvr = CPU_PPC_G2LEls, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_G2, .flags = PPC_FLAGS_G2, .msr_mask = 0x000000000007FFF3ULL, @@ -3365,45 +3583,15 @@ static ppc_def_t ppc_defs[] = { .flags = PPC_FLAGS_7x0, .msr_mask = 0x000000000007FF77ULL, }, -#if defined (TODO) - /* MPC745 (G3) */ + /* 740E (G3) */ { - .name = "745", - .pvr = CPU_PPC_74x, - .pvr_mask = 0xFFFFF000, - .insns_flags = PPC_INSNS_7x5, - .flags = PPC_FLAGS_7x5, - .msr_mask = 0x000000000007FF77ULL, - }, - { - .name = "Goldfinger", - .pvr = CPU_PPC_74x, - .pvr_mask = 0xFFFFF000, - .insns_flags = PPC_INSNS_7x5, - .flags = PPC_FLAGS_7x5, - .msr_mask = 0x000000000007FF77ULL, - }, -#endif - /* MPC750 (G3) */ - { - .name = "750", - .pvr = CPU_PPC_74x, + .name = "740e", + .pvr = CPU_PPC_740E, .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_7x0, .flags = PPC_FLAGS_7x0, .msr_mask = 0x000000000007FF77ULL, }, -#if defined (TODO) - /* MPC755 (G3) */ - { - .name = "755", - .pvr = CPU_PPC_755, - .pvr_mask = 0xFFFFF000, - .insns_flags = PPC_INSNS_7x5, - .flags = PPC_FLAGS_7x5, - .msr_mask = 0x000000000007FF77ULL, - }, -#endif /* MPC740P (G3) */ { .name = "740p", @@ -3422,16 +3610,44 @@ static ppc_def_t ppc_defs[] = { .msr_mask = 0x000000000007FF77ULL, }, #if defined (TODO) + /* MPC745 (G3) */ + { + .name = "745", + .pvr = CPU_PPC_74x, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_7x5, + .flags = PPC_FLAGS_7x5, + .msr_mask = 0x000000000007FF77ULL, + }, + { + .name = "Goldfinger", + .pvr = CPU_PPC_74x, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_7x5, + .flags = PPC_FLAGS_7x5, + .msr_mask = 0x000000000007FF77ULL, + }, +#endif +#if defined (TODO) /* MPC745P (G3) */ { .name = "745p", .pvr = CPU_PPC_74xP, - .pvr_mask = 0xFFFFF000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_7x5, .flags = PPC_FLAGS_7x5, .msr_mask = 0x000000000007FF77ULL, }, #endif + /* MPC750 (G3) */ + { + .name = "750", + .pvr = CPU_PPC_74x, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_7x0, + .flags = PPC_FLAGS_7x0, + .msr_mask = 0x000000000007FF77ULL, + }, /* MPC750P (G3) */ { .name = "750p", @@ -3441,17 +3657,15 @@ static ppc_def_t ppc_defs[] = { .flags = PPC_FLAGS_7x0, .msr_mask = 0x000000000007FF77ULL, }, -#if defined (TODO) - /* MPC755P (G3) */ + /* 750E (G3) */ { - .name = "755p", - .pvr = CPU_PPC_74xP, - .pvr_mask = 0xFFFFF000, - .insns_flags = PPC_INSNS_7x5, - .flags = PPC_FLAGS_7x5, + .name = "750e", + .pvr = CPU_PPC_750E, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_7x0, + .flags = PPC_FLAGS_7x0, .msr_mask = 0x000000000007FF77ULL, }, -#endif /* IBM 750CXe (G3 embedded) */ { .name = "750cxe", @@ -3461,6 +3675,15 @@ static ppc_def_t ppc_defs[] = { .flags = PPC_FLAGS_7x0, .msr_mask = 0x000000000007FF77ULL, }, + /* IBM 750CXr (G3 embedded) */ + { + .name = "750cxr", + .pvr = CPU_PPC_750CXR, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_7x0, + .flags = PPC_FLAGS_7x0, + .msr_mask = 0x000000000007FF77ULL, + }, /* IBM 750FX (G3 embedded) */ { .name = "750fx", @@ -3470,6 +3693,15 @@ static ppc_def_t ppc_defs[] = { .flags = PPC_FLAGS_7x0, .msr_mask = 0x000000000007FF77ULL, }, + /* IBM 750FL (G3 embedded) */ + { + .name = "750fl", + .pvr = CPU_PPC_750FL, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_7x0, + .flags = PPC_FLAGS_7x0, + .msr_mask = 0x000000000007FF77ULL, + }, /* IBM 750GX (G3 embedded) */ { .name = "750gx", @@ -3479,12 +3711,74 @@ static ppc_def_t ppc_defs[] = { .flags = PPC_FLAGS_7x0, .msr_mask = 0x000000000007FF77ULL, }, + /* IBM 750L (G3 embedded) */ + { + .name = "750l", + .pvr = CPU_PPC_750L, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_7x0, + .flags = PPC_FLAGS_7x0, + .msr_mask = 0x000000000007FF77ULL, + }, + /* IBM 750CL (G3 embedded) */ + { + .name = "750cl", + .pvr = CPU_PPC_750CL, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_7x0, + .flags = PPC_FLAGS_7x0, + .msr_mask = 0x000000000007FF77ULL, + }, +#if defined (TODO) + /* MPC755 (G3) */ + { + .name = "755", + .pvr = CPU_PPC_755, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_7x5, + .flags = PPC_FLAGS_7x5, + .msr_mask = 0x000000000007FF77ULL, + }, +#endif +#if defined (TODO) + /* MPC755D (G3) */ + { + .name = "755d", + .pvr = CPU_PPC_755D, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_7x5, + .flags = PPC_FLAGS_7x5, + .msr_mask = 0x000000000007FF77ULL, + }, +#endif +#if defined (TODO) + /* MPC755E (G3) */ + { + .name = "755e", + .pvr = CPU_PPC_755E, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_7x5, + .flags = PPC_FLAGS_7x5, + .msr_mask = 0x000000000007FF77ULL, + }, +#endif +#if defined (TODO) + /* MPC755P (G3) */ + { + .name = "755p", + .pvr = CPU_PPC_74xP, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_7x5, + .flags = PPC_FLAGS_7x5, + .msr_mask = 0x000000000007FF77ULL, + }, +#endif #if defined (TODO) /* generic G4 */ { .name = "G4", .pvr = CPU_PPC_7400, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_74xx, .flags = PPC_FLAGS_74xx, .msr_mask = 0x000000000205FF77ULL, @@ -3495,7 +3789,7 @@ static ppc_def_t ppc_defs[] = { { .name = "7400", .pvr = CPU_PPC_7400, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_74xx, .flags = PPC_FLAGS_74xx, .msr_mask = 0x000000000205FF77ULL, @@ -3503,7 +3797,7 @@ static ppc_def_t ppc_defs[] = { { .name = "Max", .pvr = CPU_PPC_7400, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_74xx, .flags = PPC_FLAGS_74xx, .msr_mask = 0x000000000205FF77ULL, @@ -3514,7 +3808,7 @@ static ppc_def_t ppc_defs[] = { { .name = "7410", .pvr = CPU_PPC_7410, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_74xx, .flags = PPC_FLAGS_74xx, .msr_mask = 0x000000000205FF77ULL, @@ -3522,22 +3816,73 @@ static ppc_def_t ppc_defs[] = { { .name = "Nitro", .pvr = CPU_PPC_7410, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_74xx, + .flags = PPC_FLAGS_74xx, + .msr_mask = 0x000000000205FF77ULL, + }, +#endif +#if defined (TODO) + /* PowerPC 7441 (G4) */ + { + .name = "7441", + .pvr = CPU_PPC_7441, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_74xx, + .flags = PPC_FLAGS_74xx, + .msr_mask = 0x000000000205FF77ULL, + }, +#endif +#if defined (TODO) + /* PowerPC 7445 (G4) */ + { + .name = "7445", + .pvr = CPU_PPC_7445, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_74xx, + .flags = PPC_FLAGS_74xx, + .msr_mask = 0x000000000205FF77ULL, + }, +#endif +#if defined (TODO) + /* PowerPC 7447 (G4) */ + { + .name = "7447", + .pvr = CPU_PPC_7447, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_74xx, + .flags = PPC_FLAGS_74xx, + .msr_mask = 0x000000000205FF77ULL, + }, +#endif +#if defined (TODO) + /* PowerPC 7447A (G4) */ + { + .name = "7447A", + .pvr = CPU_PPC_7447A, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_74xx, + .flags = PPC_FLAGS_74xx, + .msr_mask = 0x000000000205FF77ULL, + }, +#endif +#if defined (TODO) + /* PowerPC 7448 (G4) */ + { + .name = "7448", + .pvr = CPU_PPC_7448, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_74xx, .flags = PPC_FLAGS_74xx, .msr_mask = 0x000000000205FF77ULL, }, #endif - /* XXX: 7441 */ - /* XXX: 7445 */ - /* XXX: 7447 */ - /* XXX: 7447A */ #if defined (TODO) /* PowerPC 7450 (G4) */ { .name = "7450", .pvr = CPU_PPC_7450, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_74xx, .flags = PPC_FLAGS_74xx, .msr_mask = 0x000000000205FF77ULL, @@ -3545,19 +3890,51 @@ static ppc_def_t ppc_defs[] = { { .name = "Vger", .pvr = CPU_PPC_7450, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_74xx, + .flags = PPC_FLAGS_74xx, + .msr_mask = 0x000000000205FF77ULL, + }, +#endif +#if defined (TODO) + /* PowerPC 7450b (G4) */ + { + .name = "7450b", + .pvr = CPU_PPC_7450B, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_74xx, + .flags = PPC_FLAGS_74xx, + .msr_mask = 0x000000000205FF77ULL, + }, +#endif +#if defined (TODO) + /* PowerPC 7451 (G4) */ + { + .name = "7451", + .pvr = CPU_PPC_7451, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_74xx, + .flags = PPC_FLAGS_74xx, + .msr_mask = 0x000000000205FF77ULL, + }, +#endif +#if defined (TODO) + /* PowerPC 7451g (G4) */ + { + .name = "7451g", + .pvr = CPU_PPC_7451G, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_74xx, .flags = PPC_FLAGS_74xx, .msr_mask = 0x000000000205FF77ULL, }, #endif - /* XXX: 7451 */ #if defined (TODO) /* PowerPC 7455 (G4) */ { .name = "7455", .pvr = CPU_PPC_7455, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_74xx, .flags = PPC_FLAGS_74xx, .msr_mask = 0x000000000205FF77ULL, @@ -3565,7 +3942,29 @@ static ppc_def_t ppc_defs[] = { { .name = "Apollo 6", .pvr = CPU_PPC_7455, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_74xx, + .flags = PPC_FLAGS_74xx, + .msr_mask = 0x000000000205FF77ULL, + }, +#endif +#if defined (TODO) + /* PowerPC 7455F (G4) */ + { + .name = "7455f", + .pvr = CPU_PPC_7455F, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_74xx, + .flags = PPC_FLAGS_74xx, + .msr_mask = 0x000000000205FF77ULL, + }, +#endif +#if defined (TODO) + /* PowerPC 7455G (G4) */ + { + .name = "7455g", + .pvr = CPU_PPC_7455G, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_74xx, .flags = PPC_FLAGS_74xx, .msr_mask = 0x000000000205FF77ULL, @@ -3576,7 +3975,7 @@ static ppc_def_t ppc_defs[] = { { .name = "7457", .pvr = CPU_PPC_7457, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_74xx, .flags = PPC_FLAGS_74xx, .msr_mask = 0x000000000205FF77ULL, @@ -3584,7 +3983,7 @@ static ppc_def_t ppc_defs[] = { { .name = "Apollo 7", .pvr = CPU_PPC_7457, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_74xx, .flags = PPC_FLAGS_74xx, .msr_mask = 0x000000000205FF77ULL, @@ -3595,7 +3994,7 @@ static ppc_def_t ppc_defs[] = { { .name = "7457A", .pvr = CPU_PPC_7457A, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_74xx, .flags = PPC_FLAGS_74xx, .msr_mask = 0x000000000205FF77ULL, @@ -3603,7 +4002,18 @@ static ppc_def_t ppc_defs[] = { { .name = "Apollo 7 PM", .pvr = CPU_PPC_7457A, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_74xx, + .flags = PPC_FLAGS_74xx, + .msr_mask = 0x000000000205FF77ULL, + }, +#endif +#if defined (TODO) + /* PowerPC 7457C (G4) */ + { + .name = "7457c", + .pvr = CPU_PPC_7457C, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_74xx, .flags = PPC_FLAGS_74xx, .msr_mask = 0x000000000205FF77ULL, @@ -3616,7 +4026,7 @@ static ppc_def_t ppc_defs[] = { { .name = "620", .pvr = CPU_PPC_620, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_620, .flags = PPC_FLAGS_620, .msr_mask = 0x800000000005FF73ULL, @@ -3627,7 +4037,7 @@ static ppc_def_t ppc_defs[] = { { .name = "630", .pvr = CPU_PPC_630, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_630, .flags = PPC_FLAGS_630, .msr_mask = xxx, @@ -3635,7 +4045,7 @@ static ppc_def_t ppc_defs[] = { { .name = "POWER3", .pvr = CPU_PPC_630, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_630, .flags = PPC_FLAGS_630, .msr_mask = xxx, @@ -3646,7 +4056,7 @@ static ppc_def_t ppc_defs[] = { { .name = "631", .pvr = CPU_PPC_631, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_631, .flags = PPC_FLAGS_631, .msr_mask = xxx, @@ -3654,7 +4064,7 @@ static ppc_def_t ppc_defs[] = { { .name = "POWER3+", .pvr = CPU_PPC_631, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_631, .flags = PPC_FLAGS_631, .msr_mask = xxx, @@ -3665,7 +4075,7 @@ static ppc_def_t ppc_defs[] = { { .name = "POWER4", .pvr = CPU_PPC_POWER4, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_POWER4, .flags = PPC_FLAGS_POWER4, .msr_mask = xxx, @@ -3676,7 +4086,7 @@ static ppc_def_t ppc_defs[] = { { .name = "POWER4+", .pvr = CPU_PPC_POWER4P, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_POWER4, .flags = PPC_FLAGS_POWER4, .msr_mask = xxx, @@ -3687,7 +4097,7 @@ static ppc_def_t ppc_defs[] = { { .name = "POWER5", .pvr = CPU_PPC_POWER5, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_POWER5, .flags = PPC_FLAGS_POWER5, .msr_mask = xxx, @@ -3698,18 +4108,29 @@ static ppc_def_t ppc_defs[] = { { .name = "POWER5+", .pvr = CPU_PPC_POWER5P, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_POWER5, .flags = PPC_FLAGS_POWER5, .msr_mask = xxx, }, #endif #if defined (TODO) + /* POWER6 */ + { + .name = "POWER6", + .pvr = CPU_PPC_POWER6, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_POWER6, + .flags = PPC_FLAGS_POWER6, + .msr_mask = xxx, + }, +#endif +#if defined (TODO) /* PowerPC 970 */ { .name = "970", .pvr = CPU_PPC_970, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_970, .flags = PPC_FLAGS_970, .msr_mask = 0x900000000204FF36ULL, @@ -3720,13 +4141,35 @@ static ppc_def_t ppc_defs[] = { { .name = "970fx", .pvr = CPU_PPC_970FX, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_970FX, .flags = PPC_FLAGS_970FX, .msr_mask = 0x800000000204FF36ULL, }, #endif #if defined (TODO) + /* PowerPC 970MP */ + { + .name = "970MP", + .pvr = CPU_PPC_970MP, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_970, + .flags = PPC_FLAGS_970, + .msr_mask = 0x900000000204FF36ULL, + }, +#endif +#if defined (TODO) + /* PowerPC Cell */ + { + .name = "Cell", + .pvr = CPU_PPC_CELL, + .pvr_mask = 0xFFFFFFFF, + .insns_flags = PPC_INSNS_970, + .flags = PPC_FLAGS_970, + .msr_mask = 0x900000000204FF36ULL, + }, +#endif +#if defined (TODO) /* RS64 (Apache/A35) */ /* This one seems to support the whole POWER2 instruction set * and the PowerPC 64 one. @@ -3734,7 +4177,7 @@ static ppc_def_t ppc_defs[] = { { .name = "RS64", .pvr = CPU_PPC_RS64, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_RS64, .flags = PPC_FLAGS_RS64, .msr_mask = xxx, @@ -3742,7 +4185,7 @@ static ppc_def_t ppc_defs[] = { { .name = "Apache", .pvr = CPU_PPC_RS64, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_RS64, .flags = PPC_FLAGS_RS64, .msr_mask = xxx, @@ -3750,7 +4193,7 @@ static ppc_def_t ppc_defs[] = { { .name = "A35", .pvr = CPU_PPC_RS64, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_RS64, .flags = PPC_FLAGS_RS64, .msr_mask = xxx, @@ -3761,7 +4204,7 @@ static ppc_def_t ppc_defs[] = { { .name = "RS64-II", .pvr = CPU_PPC_RS64II, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_RS64, .flags = PPC_FLAGS_RS64, .msr_mask = xxx, @@ -3769,7 +4212,7 @@ static ppc_def_t ppc_defs[] = { { .name = "NortStar", .pvr = CPU_PPC_RS64II, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_RS64, .flags = PPC_FLAGS_RS64, .msr_mask = xxx, @@ -3777,7 +4220,7 @@ static ppc_def_t ppc_defs[] = { { .name = "A50", .pvr = CPU_PPC_RS64II, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_RS64, .flags = PPC_FLAGS_RS64, .msr_mask = xxx, @@ -3788,7 +4231,7 @@ static ppc_def_t ppc_defs[] = { { .name = "RS64-III", .pvr = CPU_PPC_RS64III, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_RS64, .flags = PPC_FLAGS_RS64, .msr_mask = xxx, @@ -3796,7 +4239,7 @@ static ppc_def_t ppc_defs[] = { { .name = "Pulsar", .pvr = CPU_PPC_RS64III, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_RS64, .flags = PPC_FLAGS_RS64, .msr_mask = xxx, @@ -3807,7 +4250,7 @@ static ppc_def_t ppc_defs[] = { { .name = "RS64-IV", .pvr = CPU_PPC_RS64IV, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_RS64, .flags = PPC_FLAGS_RS64, .msr_mask = xxx, @@ -3815,7 +4258,7 @@ static ppc_def_t ppc_defs[] = { { .name = "IceStar", .pvr = CPU_PPC_RS64IV, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_RS64, .flags = PPC_FLAGS_RS64, .msr_mask = xxx, @@ -3823,7 +4266,7 @@ static ppc_def_t ppc_defs[] = { { .name = "IStar", .pvr = CPU_PPC_RS64IV, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_RS64, .flags = PPC_FLAGS_RS64, .msr_mask = xxx, @@ -3831,7 +4274,7 @@ static ppc_def_t ppc_defs[] = { { .name = "SStar", .pvr = CPU_PPC_RS64IV, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_RS64, .flags = PPC_FLAGS_RS64, .msr_mask = xxx, @@ -3843,7 +4286,7 @@ static ppc_def_t ppc_defs[] = { { .name = "POWER", .pvr = CPU_POWER, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_POWER, .flags = PPC_FLAGS_POWER, .msr_mask = xxx, @@ -3855,7 +4298,7 @@ static ppc_def_t ppc_defs[] = { { .name = "POWER2", .pvr = CPU_POWER2, - .pvr_mask = 0xFFFF0000, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_POWER, .flags = PPC_FLAGS_POWER, .msr_mask = xxx, @@ -3865,8 +4308,8 @@ static ppc_def_t ppc_defs[] = { #if defined (TODO) { .name = "ppc64", - .pvr = CPU_PPC_970, - .pvr_mask = 0xFFFF0000, + .pvr = CPU_PPC_970FX, + .pvr_mask = 0xFFFFFFFF, .insns_flags = PPC_INSNS_PPC64, .flags = PPC_FLAGS_PPC64, .msr_mask = 0xA00000000204FF36ULL, |