| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2014-02-04 | milkymist-vgafb: swap pixel data in source buffer | Michael Walle | 1 | -1/+1 |
| 2014-02-04 | lm32_uart/lm32_juart: use qemu_chr_fe_write_all() | Michael Walle | 2 | -2/+2 |
| 2014-02-04 | milkymist-uart: use qemu_chr_fe_write_all() instead of qemu_chr_fe_write() | Antony Pavlov | 1 | -1/+1 |
| 2014-02-04 | tests: lm32: new rule for single test cases | Michael Walle | 1 | -4/+4 |
| 2014-02-04 | lm32_sys: increase test case name length limit | Michael Walle | 1 | -2/+3 |
| 2014-02-04 | Merge remote-tracking branch 'remotes/mcayland/qemu-openbios' into staging | Peter Maydell | 6 | -1/+1 |
| 2014-02-03 | linux-user: Fix trampoline code for CRIS | Stefan Weil | 1 | -4/+4 |
| 2014-02-03 | cris: Remove the CRIS PIC glue | Edgar E. Iglesias | 3 | -50/+0 |
| 2014-02-03 | axis-dev88: Connect the PIC upstream IRQs directly to the CPU | Edgar E. Iglesias | 1 | -4/+3 |
| 2014-02-03 | cris: Add interrupt signals to the CPU device | Edgar E. Iglesias | 2 | -0/+24 |
| 2014-02-03 | cris: Abort when a v10 takes interrupts while in a delayslot | Edgar E. Iglesias | 1 | -0/+5 |
| 2014-02-03 | cris: Add "any" as alias for "crisv32" in user emulation | Edgar E. Iglesias | 1 | -0/+6 |
| 2014-02-01 | Merge remote-tracking branch 'qmp-unstable/queue/qmp' into staging | Peter Maydell | 9 | -26/+160 |
| 2014-02-01 | Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20140131' into st... | Peter Maydell | 16 | -70/+3087 |
| 2014-02-01 | Merge remote-tracking branch 'remotes/awilliam/tags/vfio-pci-for-qemu-2014012... | Peter Maydell | 4 | -17/+77 |
| 2014-02-01 | Merge remote-tracking branch 'remotes/sstabellini/xen-140130' into staging | Peter Maydell | 1 | -2/+4 |
| 2014-01-31 | arm_gic: Fix GICD_ICPENDR and GICD_ISPENDR writes | Christoffer Dall | 1 | -1/+5 |
| 2014-01-31 | arm_gic: Introduce define for GIC_NR_SGIS | Christoffer Dall | 2 | -6/+12 |
| 2014-01-31 | target-arm: A64: Add SIMD shift by immediate | Alex Bennée | 1 | -2/+373 |
| 2014-01-31 | target-arm: A64: Add simple SIMD 3-same floating point ops | Peter Maydell | 1 | -2/+188 |
| 2014-01-31 | target-arm: A64: Add integer ops from SIMD 3-same group | Peter Maydell | 1 | -1/+164 |
| 2014-01-31 | target-arm: A64: Add logic ops from SIMD 3 same group | Peter Maydell | 1 | -1/+72 |
| 2014-01-31 | target-arm: A64: Add top level decode for SIMD 3-same group | Peter Maydell | 1 | -1/+44 |
| 2014-01-31 | target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops | Peter Maydell | 1 | -1/+130 |
| 2014-01-31 | target-arm: A64: Add SIMD three-different ABDL instructions | Peter Maydell | 1 | -2/+33 |
| 2014-01-31 | target-arm: A64: Add SIMD three-different multiply accumulate insns | Peter Maydell | 1 | -1/+232 |
| 2014-01-31 | target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTM | Will Newton | 1 | -1/+52 |
| 2014-01-31 | target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTM | Will Newton | 1 | -0/+61 |
| 2014-01-31 | target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZ | Will Newton | 1 | -1/+39 |
| 2014-01-31 | target-arm: Add set_neon_rmode helper | Will Newton | 2 | -0/+18 |
| 2014-01-31 | target-arm: Add support for AArch32 SIMD VRINTX | Will Newton | 1 | -1/+10 |
| 2014-01-31 | target-arm: Add support for AArch32 FP VRINTX | Will Newton | 1 | -0/+11 |
| 2014-01-31 | target-arm: Add support for AArch32 FP VRINTZ | Will Newton | 1 | -0/+16 |
| 2014-01-31 | target-arm: Add support for AArch32 FP VRINTR | Will Newton | 1 | -0/+11 |
| 2014-01-31 | target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTM | Will Newton | 1 | -0/+54 |
| 2014-01-31 | target-arm: Move arm_rmode_to_sf to a shared location. | Will Newton | 3 | -28/+30 |
| 2014-01-31 | display: avoid multi-statement macro | Paolo Bonzini | 4 | -29/+59 |
| 2014-01-31 | ZYNQ: Implement board MIDR control for Zynq | Alistair Francis | 1 | -0/+7 |
| 2014-01-31 | ARM: Convert MIDR to a property | Alistair Francis | 1 | -0/+1 |
| 2014-01-31 | hw/arm/boot: Don't set up ATAGS for autogenerated dtb booting | Peter Maydell | 1 | -2/+7 |
| 2014-01-31 | target-arm: A64: Add SIMD scalar copy instructions | Peter Maydell | 1 | -1/+42 |
| 2014-01-31 | target-arm: A64: Add SIMD modified immediate group | Alex Bennée | 1 | -1/+119 |
| 2014-01-31 | target-arm: A64: Add SIMD copy operations | Alex Bennée | 1 | -1/+209 |
| 2014-01-31 | target-arm: A64: Add SIMD across-lanes instructions | Michael Matz | 1 | -1/+176 |
| 2014-01-31 | target-arm: A64: Add SIMD ZIP/UZP/TRN | Michael Matz | 1 | -1/+75 |
| 2014-01-31 | target-arm: A64: Add SIMD TBL/TBLX | Michael Matz | 3 | -1/+86 |
| 2014-01-31 | target-arm: A64: Add SIMD EXT | Peter Maydell | 1 | -1/+78 |
| 2014-01-31 | target-arm: A64: Add decode skeleton for SIMD data processing insns | Alex Bennée | 1 | -1/+305 |
| 2014-01-31 | target-arm: A64: Add SIMD ld/st single | Peter Maydell | 1 | -2/+142 |
| 2014-01-31 | target-arm: A64: Add SIMD ld/st multiple | Alex Bennée | 1 | -2/+248 |
