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2014-03-05input: mouse: switch legacy handlers to new coreGerd Hoffmann1-0/+63
legacy mouse event handlers are registered in the new core, so they receive events submitted to the new input core. legacy kbd_mouse_event() continues to use the old code paths. So new-core event handlers wouldn't see events submitted via kbd_mouse_event. This leads to the constrain that we we must transition all kbd_mouse_event() users first to keep things working. But that is easier to handle than translating legacy mouse events into new-core mouse events ;) Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-03-05input: mouse: add qemu_input_is_absolute()Gerd Hoffmann2-0/+9
Same as kbd_mouse_is_absolute(), but using new input core. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-03-05input: mouse: add graphic_rotate supportGerd Hoffmann1-0/+31
Transform absolute mouse events according to graphic_rotate. Legacy input code does it for both absolute and relative events, but the logic is broken for relative coordinates, so this is most likely not used anyway. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-03-05input: mouse: add helpers functions to coreGerd Hoffmann2-0/+85
Likewise a bunch of helper functions to manage mouse button and movement events, again to make life easier for the ui code. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-03-05input: keyboard: switch curses ui to new coreGerd Hoffmann1-22/+25
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-03-05input: keyboard: switch spice ui to new coreGerd Hoffmann1-2/+20
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-03-05input: keyboard: switch vnc ui to new coreGerd Hoffmann1-19/+6
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-03-05input: keyboard: switch sdl ui to new coreGerd Hoffmann1-18/+9
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-03-05input: keyboard: switch gtk ui to new coreGerd Hoffmann1-15/+4
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-03-05input: keyboard: switch qmp_send_key() to new core.Gerd Hoffmann1-8/+3
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-03-05input: keyboard: switch legacy handlers to new coreGerd Hoffmann1-10/+56
legacy kbd event handlers are registered in the new core, so they receive events from the new input core code. keycode -> scancode translation needed here. legacy kbd_put_keycode() sends events to the new core. scancode -> keycode translation needed here. So with this patch the new input core is fully functional for keyboard events. New + legacy interfaces can be mixed in any way. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-03-05input: keyboard: add helper functions to coreGerd Hoffmann2-0/+40
A bunch of helper functions to manage keyboard events, to make life simpler for the ui code when submitting keyboard events. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-03-05input: add core bits of the new input layerGerd Hoffmann3-1/+116
Register and unregister handlers. Event dispatcher code. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-03-05input: qapi: add pause keyGerd Hoffmann1-2/+2
It's missing. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2014-03-05input: qapi: add unmapped keyGerd Hoffmann1-1/+4
Simplifies building something -> QkeyCode mapping tables. Uninitialized entries can easily identified then. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2014-03-05input: qapi: define event typesGerd Hoffmann1-0/+76
Define input event types, using qapi. So we get nicely autogenerated types for our input events. And when it comes to qmp support some day things will be a lot easier. Types are modeled after the linux input layer. There are separate event types for each value. There is a sync to indicate the end of a event group. Mouse events are split into motion events (one for each axis) and button events, which are grouped by sync. Keyboard events are using the existing KeyValue type. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2014-03-05input: rename file to legacyGerd Hoffmann2-1/+1
Rename ui/input.c to ui/input-legacy.c. We are going to replace it step by step. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-03-05console: export QemuConsole index,width,heightGerd Hoffmann2-0/+27
Add functions to query QemuConsole properties. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2014-03-05s390x/virtio-ccw: Adapter interrupt support.Cornelia Huck7-9/+120
Handle the new CCW_CMD_SET_IND_ADAPTER command enabling adapter interrupts on guest request. When active, host->guest notifications will be handled via global_indicator -> queue indicators instead of queue indicators + subchannel I/O interrupt. Indicators for virtqueues may be present at an offset. Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2014-03-05target-ppc: spapr: e500: fix to use cpu_dt_idAlexey Kardashevskiy9-25/+41
This makes use of @cpu_dt_id and related API in: 1. emulated XICS hypercall handlers as they receive fixed CPU indexes; 2. XICS-KVM to enable in-kernel XICS on right CPU; 3. device-tree renderer. This removes @cpu_index fixup as @cpu_dt_id is used instead so QEMU monitor can accept command-line CPU indexes again. This changes kvm_arch_vcpu_id() to use ppc_get_vcpu_dt_id() as at the moment KVM CPU id and device tree ID are calculated using the same algorithm. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Acked-by: Mike Day <ncmike@ncultra.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: add PowerPCCPU::cpu_dt_idAlexey Kardashevskiy6-25/+46
Normally CPUState::cpu_index is used to pick the right CPU for various operations. However default consecutive numbering does not always work for POWERPC. These indexes are reflected in /proc/device-tree/cpus/PowerPC,POWER7@XX and used to call KVM VCPU's ioctls. In order to achieve this, kvmppc_fixup_cpu() was introduced. Roughly speaking, it multiplies cpu_index by the number of threads per core. This approach has disadvantages such as: 1. NUMA configuration stays broken after the fixup; 2. CPU-targeted commands from the QEMU Monitor do not work properly as CPU indexes have been fixed and there is no clear way for the user to know what the new CPU indexes are. This introduces a @cpu_dt_id field in the CPUPPCState struct which is initialized from @cpu_index by default and can be fixed later to meet the device tree requirements. This adds an API to handle @cpu_dt_id. This removes kvmppc_fixup_cpu() as it is not more needed, @cpu_dt_id is calculated in ppc_cpu_realize(). This will be used later in machine code. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Acked-by: Mike Day <ncmike@ncultra.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Introduce hypervisor call H_GET_TCELaurent Dufour2-0/+38
This patch introduces the hypervisor call H_GET_TCE which is basically the reverse of H_PUT_TCE, as defined in the Power Architecture Platform Requirements (PAPR). The hcall H_GET_TCE is required by the kdump kernel which is calling it to retrieve the TCE set up by the panicing kernel. Signed-off-by: Laurent Dufour <ldufour@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Update ppc_hash64_store_hpte to support updating in-kernel htabAneesh Kumar K.V4-15/+68
This support updating htab managed by the hypervisor. Currently we don't have any user for this feature. This actually bring the store_hpte interface in-line with the load_hpte one. We may want to use this when we want to emulate henter hcall in qemu for HV kvm. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> [ folded fix for the "warn_unused_result" build break in kvmppc_hash64_write_pte(), Greg Kurz <gkurz@linux.vnet.ibm.com> ] Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Change the hpte store APIAneesh Kumar K.V3-31/+16
For updating in kernel htab we need to provide both pte0 and pte1, hence update the interface to take pte0 and pte1 together Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> [ ldq_phys() API change, Greg Kurz <gkurz@linux.vnet.ibm.com> ] Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Fix page table lookup with kvm enabledAneesh Kumar K.V6-40/+184
With kvm enabled, we store the hash page table information in the hypervisor. Use ioctl to read the htab contents. Without this we get the below error when trying to read the guest address (gdb) x/10 do_fork 0xc000000000098660 <do_fork>: Cannot access memory at address 0xc000000000098660 (gdb) Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> [ fixes for 32 bit build (casts!), ldq_phys() API change, Greg Kurz <gkurz@linux.vnet.ibm.com ] Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Fix htab_mask calculationAneesh Kumar K.V8-14/+40
Correctly update the htab_mask using the return value of KVM_PPC_ALLOCATE_HTAB ioctl. Also we don't update sdr1 on GET_SREGS for HV. We check for external htab and if found true, we don't need to update sdr1 Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> [ fixed pte group offset computation in ppc_hash64_htab_lookup() that caused TCG to fail, Greg Kurz <gkurz@linux.vnet.ibm.com> ] Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Use Additional Temporary in stqcx CaseTom Musta1-3/+5
Per Alex Graf's suggestion, the recently added case to gen_conditional_store for stqcx should use an additional temporary when accessing the second doubleword. This avoids the mutation of the EA argument to the function, which is counter intuitive. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Fix Compiler Warnings Due to 64-Bit Constants Declared as ULTom Musta1-22/+22
This patch fixes 64 bit constants that were erroneously declared as "ul" instead of "ull". The preferred form "ULL" is used. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05PPC: sPAPR: Only use getpagesize() when we run with kvmAlexander Graf1-1/+12
We currently size the msi window trap page according to the host's page size so that we poke a working hole into a memory slot in case we overlap. However, this is only ever necessary with KVM active. Without KVM, we should rather try to be host platform agnostic and use a constant size: 4k. This fixes a build breakage on win32 hosts. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc/translate.c: Use ULL suffix for 64 bit constantsPeter Maydell1-2/+2
64 bit constants need the "ULL" suffix, not just "UL", because on 32 bit platforms 'long' is not large enough and this will cause a compiler warning. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05spapr-vlan: flush queue whenever can_receive can go from false to trueAlexey Kardashevskiy1-0/+2
When the guests adds buffers to receive queue, the network device should flush its queue of pending packets. This is done with qemu_flush_queued_packets. This adds a call to qemu_flush_queued_packets() which wakes up the main loop and let QEMU update the network device status which now is "can receive". The patch basically does the same thing as e8b4c68 does. Suggested-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Vector Permute and Exclusive ORTom Musta3-1/+21
This patch adds the Vector Permuate and Exclusive OR (vpermxor) instruction introduced in Power ISA Version 2.07. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Vector SHA Sigma InstructionsTom Musta3-0/+108
This patch adds the Vector SHA Sigma instructions introduced in Power ISA Version 2.07: - Vector SHA-512 Sigma Doubleword (vshasigmad) - Vector SHA-256 Sigma Word (vshasigmaw) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: AES InstructionsTom Musta3-0/+315
This patch adds the Vector AES instructions introduced in Power ISA Version 2.07: - Vector AES Cipher (vcipher) - Vector AES Cipher Last (vcipherlast) - Vector AES Inverse Cipher (vncipher) - Vector AES Inverse Cipher Last (vncipherlast) - Vector AES SubBytes (vsbox) Note that the implementation of vncipher deviates from the RTL in ISA V2.07. However it does match the verbal description in the third paragraph. The RTL will be fixed in ISA V2.07B. The implementation here has been tested against actual P8 hardware. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Binary Coded Decimal InstructionsTom Musta3-4/+245
This patch add the Binary Coded Decimal instructions bcdadd. and bcdsub. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Vector Polynomial Multiply SumTom Musta3-0/+82
This patch adds the Vectory Polynomial Multiply Sum instructions introduced in Power ISA Version 2.07: - Vectory Polynomial Multiply Sum Byte (vpmsumb) - Vectory Polynomial Multiply Sum Halfword (vpmsumh) - Vectory Polynomial Multiply Sum Word (vpmsumw) - Vectory Polynomial Multiply Sum Doubleword (vpmsumd) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Vector Gather Bits by BytesTom Musta3-0/+279
This patch adds the Vector Gather Bits by Bytes Doubleword (vgbbd) instruction which is introduced in Power ISA Version 2.07. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Doubleword ComparesTom Musta3-7/+29
This patch adds the Vector Compare Doubleword instructions introduced by Power ISA Version 2.07: - Vector Compare Equal to Unsigned Doubleword (vcmpequd) - Vector Compare Greater Than Signed Doubleword (vcmpgtsd) - Vector Compare Greater Than Unsigned Doubleword (vcmpgtud) These instructions are encoded with bit 31 set to 1 and so are duals with vcmpeqfp, vcmpgtfp and vcmpbfp respectively. The helper macro for integer compares is enhanced to account for 64-bit operands. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: vbpermq InstructionTom Musta3-0/+34
This patch adds the Vector Bit Permute Quadword (vbpermq) instruction introduced in Power ISA Version 2.07. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Quadword Addition and SubtracationTom Musta3-0/+211
This patch adds the Vector Quadword Addition and Subtraction instructions introduced in Power ISA Version 2.07: - Vector Add Unsigned Quadword Modulo (vadduqm) - Vector Add & Write Carry Unsigned Quadword (vaddcuq) - Vector Add Extended Unsigned Quadword (vaddeuqm) - Vector Add Extended & Write Carry Unsigned Quadword (vaddecuq) - Vector Subtract Unsigned Quadword Modulo (vsubuqm) - Vector Subtract & Write Carry Unsigned Quadword (vsubcuq) - Vector Subtract Extended Unsigned Quadword (vsubeuqm) - Vector Subtract Extended & Write Carry Unsigned Quadword (vsubecuq) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Vector Doubleword Rotate and Shift InstructionsTom Musta3-0/+16
This patch adds the vector doublword rotate and shift instructions introduced in Power ISA Version 2.07: - Vector Rotate Left Doubleword instruction (vrld) - Vector Shift Left Doubleword (vsld) - Vector Shift Right Doubleword (vsrd) - Vector Shift Right Algegbraic Doubleword (vsrad) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Change Bit Masks to Support 64-bit Rotates and ShiftsTom Musta1-25/+15
Existing code in the VROTATE, VSL and VSR macros for the Altivec rotate and shift helpers uses a formula to compute a bit mask used to extract the rotate/shift amount from the VRB register. What is desired is: mask = (1 << (3 + log2(sizeof(element)))) - 1 but what is implemented is: mask = (1 << (3 + (sizeof(element)/2))) - 1 This produces correct answers when "element" is uint8_t, uint16_t or uint_32t. But it breaks down when element is uint64_t. This patch corrects the situation. Since the mask is known at compile time, the macros are changed to simply accept the mask as an argument. Subsequent patches in this series will add double-word variants of rotates and shifts and thus take advantage of this fix. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Vector Merge InstructionsTom Musta1-0/+37
This patch adds the Vector Merge Even Word (vmrgew) and Vector Merge Odd Word (vmrgow) instructions introduced in Power ISA Version 2.07. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Unpack Signed Word InstructionsTom Musta3-0/+8
This patch adds the Unpack Signed Word instructions introduced in Power ISA Version 2.07: - Vector Unpack High Signed Word (vupkusw) - Vector Unpack Low Signed Word (vupklsw) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Pack Doubleword InstructionsTom Musta3-0/+16
This patch adds the Vector Pack Doubleword instructions introduced in Power ISA Version 2.07: - Vector Pack Signed Doubleword Signed Saturate (vpksdss) - Vector Pack Signed Doubleword Unsigned Saturate (vpksdus) - Vector Pack Unsigned Doubleword Unsigned Modulo (vpkudum) - Vector Pack Unsigned Doubleword Unsigned Saturate (vpkudus) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Vector Min/Max Doubleword InstructionsTom Musta3-0/+14
This patch adds the Vector Minimum and Maximum Doubleword instructions that are introduced in Power ISA Version 2.07. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Vector Population Count InstructionsTom Musta3-4/+36
This patch adds the Vector Population Count instructions introduced in Power ISA Version 2.07: vpopcntb, vpopcnth, vpopcntw and vpopcntd. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Add Vector Count Leading ZeroesTom Musta3-0/+43
This patch adds the Vector Count Leading Zeroes instructions introduced in Power ISA Version 2.07 - vclzb, vclzh, vclzw and vclzd. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: vmuluw InstructionTom Musta3-1/+6
This patch adds the Vector Multiply Unsigned Word Modulo (vmuluwm) instruction. The existing VARITH_DO macro is re-used to (trivially) instantiate the helper code. Since bits 21-31 of any vmuluwm instruction is 137, the instruction is coded as a dual to vmulouw (bits 21-31 = 136). Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Altivec 2.07: Multiply Even/Odd Word InstructionsTom Musta3-0/+14
This patch adds the Multilpy Even/Odd Word instructions that are introduced in Power ISA Version 2.07: - Vector Multiply Even Unsigned Word (vmuleuw) - Vector Multiply Even Signed Word (vmulesw) - Vector Multiply Odd Unsigned Word (vmulouw) - Vector Multiply Odd Signed Word (vmulosw) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
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