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2014-01-10Merge remote-tracking branch 'afaerber/tags/qom-cpu-for-anthony' into stagingAnthony Liguori12-113/+118
QOM CPUState refactorings / X86CPU * TLB invalidation optimizations * X86CPU initialization cleanups * Preparations for X86CPU hot-unplug # gpg: Signature made Tue 24 Dec 2013 04:51:52 AM PST using RSA key ID 3E7E013F # gpg: Good signature from "Andreas Färber <afaerber@suse.de>" # gpg: aka "Andreas Färber <afaerber@suse.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 174F 0347 1BCC 221A 6175 6F96 FA2E D12D 3E7E 013F * afaerber/tags/qom-cpu-for-anthony: target-i386: Cleanup 'foo=val' feature handling target-i386: Cleanup 'foo' feature handling target-i386: Convert 'check' and 'enforce' to static properties target-i386: Convert 'hv_spinlocks' to static property target-i386: Convert 'hv_vapic' to static property target-i386: Convert 'hv_relaxed' to static property cpu-exec: Optimize X86CPU usage in cpu_exec() target-i386: Move apic_state field from CPUX86State to X86CPU cputlb: Tidy memset() of arrays cputlb: Use memset() when flushing entries
2014-01-10Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20140107' into ↵Anthony Liguori0-0/+0
staging target-arm queue: * further A64 decoder patches, including enabling the aarch64-linux-user target; this includes full floating point support. Neon is not yet supported. * cadence UART model fixes. * some minor bug fixes and cleanups. * all the softfloat fixes required by the new A64 instructions; several of these will also be used by PPC. * pmaydell/tags/pull-target-arm-20140107: (61 commits) target-arm: A64: Add support for FCVT between half, single and double target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructions target-arm: A64: Add floating-point<->integer conversion instructions target-arm: A64: Add floating-point<->fixed-point instructions target-arm: A64: Add extra VFP fixed point conversion helpers target-arm: Ignore most exceptions from scalbn when doing fixpoint conversion target-arm: Rename A32 VFP conversion helpers target-arm: Prepare VFP_CONV_FIX helpers for A64 uses softfloat: Add support for ties-away rounding softfloat: Refactor code handling various rounding modes softfloat: Add float16 <=> float64 conversion functions softfloat: Factor out RoundAndPackFloat16 and NormalizeFloat16Subnormal softfloat: Provide complete set of accessors for fp state softfloat: Fix float64_to_uint32_round_to_zero softfloat: Fix float64_to_uint32 softfloat: Fix float64_to_uint64_round_to_zero softfloat: Add float32_to_uint64() softfloat: Fix factor 2 error for scalbn on denormal inputs softfloat: Only raise Invalid when conversions to int are out of range softfloat: Fix float64_to_uint64 ... Conflicts: target-arm/cpu.h aliguori: resolved trivial conflict Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2014-01-10Merge remote-tracking branch 'riku/linux-user-for-upstream' into stagingAnthony Liguori6-10/+23
* riku/linux-user-for-upstream: linux-user: Remove regs parameter of load_elf_binary and load_flt_binary linux-user: Support the accept4 socketcall Message-id: 1389364137-23287-1-git-send-email-riku.voipio@linaro.org Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2014-01-10linux-user: Remove regs parameter of load_elf_binary and load_flt_binaryWill Newton4-10/+6
The regs parameter is not used anywhere, so remove it. Signed-off-by: Will Newton <will.newton@linaro.org> Reviewed-by: Erik de Castro Lopo <erikd@mega-nerd.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
2014-01-10linux-user: Support the accept4 socketcallAndré Hentschel2-0/+17
Cc: Riku Voipio <riku.voipio@iki.fi> Signed-off-by: André Hentschel <nerv@dawncrow.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Erik de Castro Lopo <erikd@mega-nerd.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
2014-01-09Merge remote-tracking branch 'otubo/seccomp' into stagingAnthony Liguori1-0/+1
* otubo/seccomp: seccomp: exit if seccomp_init() fails Message-id: 1387565447-24241-1-git-send-email-otubo@linux.vnet.ibm.com Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2014-01-09Merge remote-tracking branch 'rth/ldst-i386-2' into stagingAnthony Liguori2-1551/+1130
* rth/ldst-i386-2: (49 commits) target-i386: Tidy ljmp target-i386: Rename gen_op_jmp_T0 to gen_op_jmp_v target-i386: Tidy some size computation target-i386: Remove gen_op_mov_reg_A0 target-i386: Remove gen_op_mov_TN_reg target-i386: Remove gen_op_addl_T0_T1 target-i386: Remove gen_op_mov_reg_T1 target-i386: Remove gen_op_mov_reg_T0 target-i386: Tidy cpu_regs initialization target_i386: Clean up gen_pop_T0 target-i386: Combine gen_push_T* into gen_push_v target-i386: Tidy addr16 code in gen_lea_modrm target-i386: Change dflag to TCGMemOp target-i386: Change gen_op_mov_reg_A0 size parameter to TCGMemOp target-i386: Change aflag to TCGMemOp target-i386: Change gen_op_j*z_ecx size parameter to TCGMemOp target-i386: Change gen_op_add_reg_* size parameter to TCGMemOp target-i386: Use TCGMemOp for 'ot' variables target-i386: Remove gen_op_andl_A0_ffff target-i386: Remove gen_op_movl_T0_T1 ... Message-id: 1389128439-10067-1-git-send-email-rth@twiddle.net Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2014-01-09Merge remote-tracking branch 'afaerber/tags/qom-devices-for-anthony' into ↵Anthony Liguori84-183/+493
staging QOM infrastructure fixes and device conversions * QOM interface fixes and unit test * Device no_user sanitization and documentation * Device error reporting improvement * Conversion of APIC, ICC, IOAPIC to QOM realization model # gpg: Signature made Tue 24 Dec 2013 09:04:05 AM PST using RSA key ID 3E7E013F # gpg: Good signature from "Andreas Färber <afaerber@suse.de>" # gpg: aka "Andreas Färber <afaerber@suse.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 174F 0347 1BCC 221A 6175 6F96 FA2E D12D 3E7E 013F * afaerber/tags/qom-devices-for-anthony: (24 commits) qdev-monitor: Improve error message for -device nonexistant ioapic: QOM'ify ioapic ioapic: Cleanup for QOM'ification icc_bus: QOM'ify ICC apic: QOM'ify APIC apic: Cleanup for QOM'ification qdev: Drop misleading qbus_free() function qom: Detect bad reentrance during object_class_foreach() tests: Test QOM interface casting qom: Do not register interface "types" in the type table and fix names qom: Split out object and class caches qdev: Document that pointer properties kill device_add hw: cannot_instantiate_with_device_add_yet due to pointer props qdev-monitor: Avoid device_add crashing on non-device driver name qdev: Do not let the user try to device_add when it cannot work isa: Clean up use of cannot_instantiate_with_device_add_yet vt82c686: Clean up use of cannot_instantiate_with_device_add_yet piix3 piix4: Clean up use of cannot_instantiate_with_device_add_yet ich9: Document why cannot_instantiate_with_device_add_yet pci-host: Consistently set cannot_instantiate_with_device_add_yet ...
2014-01-09Merge remote-tracking branch 'mjt/trivial-patches' into stagingAnthony Liguori18-218/+233
* mjt/trivial-patches: acpi unit-test: Remove temporary disk after test mainstone: Fix duplicate array values for key 'space' pxa27x: Add 'const' attribute to keyboard maps pxa27x: Reduce size of keyboard matrix mapping doc: Mention chardev:id in available devices for -serial configure: Python tests must be done before help message configure: Rewrite code for help message fix -boot strict regressed in commit 6ef4716 vl: make boot_strict variable static (not used outside vl.c) x86: only allow real mode to access 32bit without LMA linux-user: Use macro TARGET_NSIG_WORDS where possible exynos4210: Use macro ARRAY_SIZE where possible ui/cocoa: Use macro ARRAY_SIZE where possible misc: Use macro ARRAY_SIZE where possible openrisc: Fix spelling in comment (transaltion -> translation) hw/arm/highbank: Simplify code (memory region in device state) Message-id: 1388182050-10270-1-git-send-email-mjt@msgid.tls.msk.ru Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2014-01-09Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20140108' into ↵Anthony Liguori27-667/+4504
staging target-arm queue: * further A64 decoder patches, including enabling the aarch64-linux-user target; this includes full floating point support. Neon is not yet supported. * cadence UART model fixes. * some minor bug fixes and cleanups. * all the softfloat fixes required by the new A64 instructions; several of these will also be used by PPC. # gpg: Signature made Wed 08 Jan 2014 11:25:12 AM PST using RSA key ID 14360CDE # gpg: Can't check signature: public key not found * pmaydell/tags/pull-target-arm-20140108: (76 commits) target-arm: A64: Add support for FCVT between half, single and double target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructions target-arm: A64: Add floating-point<->integer conversion instructions target-arm: A64: Add floating-point<->fixed-point instructions target-arm: A64: Add extra VFP fixed point conversion helpers target-arm: Ignore most exceptions from scalbn when doing fixpoint conversion target-arm: Rename A32 VFP conversion helpers target-arm: Prepare VFP_CONV_FIX helpers for A64 uses softfloat: Add support for ties-away rounding softfloat: Refactor code handling various rounding modes softfloat: Add float16 <=> float64 conversion functions softfloat: Factor out RoundAndPackFloat16 and NormalizeFloat16Subnormal softfloat: Provide complete set of accessors for fp state softfloat: Fix float64_to_uint32_round_to_zero softfloat: Fix float64_to_uint32 softfloat: Fix float64_to_uint64_round_to_zero softfloat: Add float32_to_uint64() softfloat: Fix factor 2 error for scalbn on denormal inputs softfloat: Only raise Invalid when conversions to int are out of range softfloat: Fix float64_to_uint64 ... Message-id: 1389209439-25448-1-git-send-email-peter.maydell@linaro.org Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2014-01-08target-arm: A64: Add support for FCVT between half, single and doublePeter Maydell3-1/+96
Add support for FCVT between half, single and double precision. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructionsPeter Maydell3-1/+191
This patch adds support for those instructions in the "Floating-point data-processing (1 source)" group which are simple 32-bit-to-32-bit or 64-bit-to-64-bit operations (ie everything except FCVT between single/double/half precision). We put the new round-to-int helpers in helper.c because they will also be used by the new ARMv8 A32/T32 rounding instructions. Signed-off-by: Alexander Graf <agraf@suse.de> [WN: Commit message tweak, merged single and double precision patches, updated to new infrastructure.] Signed-off-by: Will Newton <will.newton@linaro.org> [PMM: reworked decode, split FCVT out into their own patch] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08target-arm: A64: Add floating-point<->integer conversion instructionsWill Newton1-3/+20
Add support for the AArch64 floating-point <-> integer conversion instructions to disas_fpintconv. In the process we can rearrange and simplify the detection of unallocated encodings a little. We also correct a typo in the instruction encoding diagram for this instruction group: bit 21 is 1, not 0. Signed-off-by: Will Newton <will.newton@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08target-arm: A64: Add floating-point<->fixed-point instructionsAlexander Graf3-1/+200
This patch adds emulation for the instruction group labeled "Floating-point <-> fixed-point conversions" in the ARM ARM. Namely this includes the instructions SCVTF, UCVTF, FCVTZS, FCVTZU (scalar, fixed-point). Signed-off-by: Alexander Graf <agraf@suse.de> [WN: Commit message tweak, rebased, updated to new infrastructure. Applied bug fixes from Michael Matz and Janne Grunau.] Signed-off-by: Will Newton <will.newton@linaro.org> [PMM: significant cleanup] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08target-arm: A64: Add extra VFP fixed point conversion helpersWill Newton2-1/+26
Define the full set of floating point to fixed point conversion helpers required to support AArch64. Signed-off-by: Will Newton <will.newton@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08target-arm: Ignore most exceptions from scalbn when doing fixpoint conversionPeter Maydell1-0/+9
The VFP fixed point conversion helpers first call float_scalbn and then convert the result to an integer. This scalbn operation may set floating point exception flags for: * overflow & inexact (if it overflows to infinity) * input denormal squashed to zero * output denormal squashed to zero Of these, we only care about the input-denormal flag, since the output of the whole scale-and-convert operation will be an integer (so squashed-output-denormal and overflow don't apply). Suppress the others by saving the pre-scalb exception flags and only copying across a potential input-denormal flag. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08target-arm: Rename A32 VFP conversion helpersWill Newton3-24/+35
The VFP conversion helpers for A32 round to zero as this is the only rounding mode supported. Rename these helpers to make it clear that they round to zero and are not suitable for use in the AArch64 code. Signed-off-by: Will Newton <will.newton@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08target-arm: Prepare VFP_CONV_FIX helpers for A64 usesWill Newton1-14/+14
Make the VFP_CONV_FIX helpers a little more flexible in preparation for the A64 uses. This requires two changes: * use the correct softfloat conversion function based on itype rather than always the int32 one; this is possible now that softfloat provides int16 versions and necessary for the future conversion-to-int64 A64 variants. This also allows us to drop the awkward 'sign' macro argument. * split the 'fsz' argument which currently controls both width of the input float type and width of the output integer type into two; this will allow us to specify the A64 64-bit-int-to-single conversion function, where the two widths are different. We can also drop the (itype##_t) cast now that softfloat guarantees that all the itype##_to_float* functions take an integer argument of exactly the correct type. Signed-off-by: Will Newton <will.newton@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08softfloat: Add support for ties-away roundingPeter Maydell2-1/+56
IEEE754-2008 specifies a new rounding mode: "roundTiesToAway: the floating-point number nearest to the infinitely precise result shall be delivered; if the two nearest floating-point numbers bracketing an unrepresentable infinitely precise result are equally near, the one with larger magnitude shall be delivered." Implement this new mode (it is needed for ARM). The general principle is that the required code is exactly like the ties-to-even code, except that we do not need to do the "in case of exact tie clear LSB to round-to-even", because the rounding operation naturally causes the exact tie to round up in magnitude. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08softfloat: Refactor code handling various rounding modesPeter Maydell1-164/+241
Refactor the code in various functions which calculates rounding increments given the current rounding mode, so that instead of a set of nested if statements we have a simple switch statement. This will give us a clean place to add the case for the new tiesAway rounding mode. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08softfloat: Add float16 <=> float64 conversion functionsPeter Maydell2-0/+77
Add the conversion functions float16_to_float64() and float64_to_float16(), which will be needed for the ARM A64 instruction set. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08softfloat: Factor out RoundAndPackFloat16 and NormalizeFloat16SubnormalPeter Maydell1-84/+125
In preparation for adding conversions between float16 and float64, factor out code currently done inline in the float16<=>float32 conversion functions into functions RoundAndPackFloat16 and NormalizeFloat16Subnormal along the lines of the existing versions for the other float types. Note that we change the handling of zExp from the inline code to match the API of the other RoundAndPackFloat functions; however we leave the positioning of the binary point between bits 22 and 23 rather than shifting it up to the high end of the word. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08softfloat: Provide complete set of accessors for fp statePeter Maydell2-18/+36
Tidy up the get/set accessors for the fp state to add missing ones and make them all inline in softfloat.h rather than some inline and some not. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08softfloat: Fix float64_to_uint32_round_to_zeroTom Musta1-8/+7
The float64_to_uint32_round_to_zero routine is incorrect. For example, the following test pattern: 425F81378DC0CD1F / 0x1.f81378dc0cd1fp+38 will erroneously set the inexact flag. This patch re-implements the routine to use the float64_to_uint64_round_to_zero routine. If saturation occurs we ignore any flags set by the conversion function and raise only Invalid. This contribution can be licensed under either the softfloat-2a or -2b license. Signed-off-by: Tom Musta <tommusta@gmail.com> Message-id: 1387397961-4894-6-git-send-email-tommusta@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08softfloat: Fix float64_to_uint32Tom Musta1-8/+7
The float64_to_uint32 has several flaws: - for numbers between 2**32 and 2**64, the inexact exception flag may get incorrectly set. In this case, only the invalid flag should be set. test pattern: 425F81378DC0CD1F / 0x1.f81378dc0cd1fp+38 - for numbers between 2**63 and 2**64, incorrect results may be produced: test pattern: 43EAAF73F1F0B8BD / 0x1.aaf73f1f0b8bdp+63 This patch re-implements float64_to_uint32 to re-use the float64_to_uint64 routine (instead of float64_to_int64). For the saturation case, we ignore any flags which the conversion routine has set and raise only the invalid flag. This contribution can be licensed under either the softfloat-2a or -2b license. Signed-off-by: Tom Musta <tommusta@gmail.com> Message-id: 1387397961-4894-5-git-send-email-tommusta@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08softfloat: Fix float64_to_uint64_round_to_zeroTom Musta1-7/+5
The float64_to_uint64_round_to_zero routine is incorrect. For example, the following test pattern: 46697351FF4AEC29 / 0x1.97351ff4aec29p+103 currently produces 8000000000000000 instead of FFFFFFFFFFFFFFFF. This patch re-implements the routine to temporarily force the rounding mode and use the float64_to_uint64 routine. This contribution can be licensed under either the softfloat-2a or -2b license. Signed-off-by: Tom Musta <tommusta@gmail.com> Message-id: 1387397961-4894-4-git-send-email-tommusta@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08softfloat: Add float32_to_uint64()Tom Musta2-0/+47
This patch adds the float32_to_uint64() routine, which converts a 32-bit floating point number to an unsigned 64 bit number. This contribution can be licensed under either the softfloat-2a or -2b license. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: removed harmless but silly int64_t casts] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08softfloat: Fix factor 2 error for scalbn on denormal inputsPeter Maydell1-8/+21
If the input to float*_scalbn() is denormal then it represents a number 0.[mantissabits] * 2^(1-exponentbias) (and the actual exponent field is all zeroes). This means that when we convert it to our unpacked encoding the unpacked exponent must be one greater than for a normal number, which represents 1.[mantissabits] * 2^(e-exponentbias) for an exponent field e. This meant we were giving answers too small by a factor of 2 for all denormal inputs. Note that the float-to-int routines also have this behaviour of not adjusting the exponent for denormals; however there it is harmless because denormals will all convert to integer zero anyway. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08softfloat: Only raise Invalid when conversions to int are out of rangePeter Maydell1-12/+16
We implement a number of float-to-integer conversions using conversion to an integer type with a wider range and then a check against the narrower range we are actually converting to. If we find the result to be out of range we correctly raise the Invalid exception, but we must also suppress other exceptions which might have been raised by the conversion function we called. This won't throw away exceptions we should have preserved, because for the 'core' exception flags the IEEE spec mandates that the only valid combinations of exception that can be raised by a single operation are Inexact + Overflow and Inexact + Underflow. For the non-IEEE softfloat flag for input denormals, we can guarantee that that flag won't have been set for out of range float-to-int conversions because a squashed denormal by definition goes to plus or minus zero, which is always in range after conversion to integer zero. This bug has been fixed for some of the float-to-int conversion routines by previous patches; fix it for the remaining functions as well, so that they all restore the pre-conversion status flags prior to raising Invalid. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08softfloat: Fix float64_to_uint64Tom Musta1-8/+93
The comment preceding the float64_to_uint64 routine suggests that the implementation is broken. And this is, indeed, the case. This patch properly implements the conversion of a 64-bit floating point number to an unsigned, 64 bit integer. This contribution can be licensed under either the softfloat-2a or -2b license. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08softfloat: Make the int-to-float functions take exact-width typesPeter Maydell2-26/+26
Currently the int-to-float functions take types which are specified as "at least X bits wide", rather than "exactly X bits wide". This is confusing and unhelpful since it means that the callers have to include an explicit cast to [u]intXX_t to ensure the correct behaviour. Fix them all to take the exactly-X-bits-wide types instead. Note that this doesn't change behaviour at all since at the moment we happen to define the 'int32' and 'uint32' types as exactly 32 bits wide, and the 'int64' and 'uint64' types as exactly 64 bits wide. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08softfloat: Add 16 bit integer to float conversionsPeter Maydell1-0/+21
Add the float to 16 bit integer conversion routines. These can be trivially implemented in terms of the int32_to_float* routines, but providing them makes our API more symmetrical and can simplify callers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08softfloat: Add float to 16bit integer conversions.Will Newton2-0/+84
ARMv8 requires support for converting 32 and 64bit floating point values to signed and unsigned 16bit integers. Signed-off-by: Will Newton <will.newton@linaro.org> [PMM: updated not to incorrectly set Inexact for Invalid inputs] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08softfloat: Fix exception flag handling for float32_to_float16()Peter Maydell1-39/+66
Our float32 to float16 conversion routine was generating the correct numerical answers, but not always setting the right set of exception flags. Fix this, mostly by rearranging the code to more closely resemble RoundAndPackFloat*, and in particular: * non-IEEE halfprec always raises Invalid for input NaNs * we need to check for the overflow case before underflow * we weren't getting the tininess-detected-after-rounding case correct (somewhat academic since only ARM uses halfprec and it is always tininess-detected-before-rounding) * non-IEEE halfprec overflow raises only Invalid, not Invalid + Inexact * we weren't setting Inexact when we should Also add some clarifying comments about what the code is doing. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-08hw: arm_gic: Introduce gic_set_priority functionChristoffer Dall2-5/+11
To make the code slightly cleaner to look at and make the save/restore code easier to understand, introduce this function to set the priority of interrupts. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1387606179-22709-3-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-08arm_gic: Rename GIC_X_TRIGGER to GIC_X_EDGE_TRIGGERChristoffer Dall4-12/+12
TRIGGER can really mean mean anything (e.g. was it triggered, is it level-triggered, is it edge-triggered, etc.). Rename to EDGE_TRIGGER to make the code comprehensible without looking up the data structure. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1387606179-22709-2-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-08target-arm: fix build with gcc 4.8.2Michael S. Tsirkin1-0/+6
commit 5ce4f35781028ce1aee3341e6002f925fdc7aaf3 "target-arm: A64: add set_pc cpu method" introduces an array aarch64_cpus which is zero size if this code is built without CONFIG_USER_ONLY. In particular an attempt to iterate over this array produces a warning under gcc 4.8.2: CC aarch64-softmmu/target-arm/cpu64.o /scm/qemu/target-arm/cpu64.c: In function ‘aarch64_cpu_register_types’: /scm/qemu/target-arm/cpu64.c:124:5: error: comparison of unsigned expression < 0 is always false [-Werror=type-limits] for (i = 0; i < ARRAY_SIZE(aarch64_cpus); i++) { ^ cc1: all warnings being treated as errors This is the result of ARRAY_SIZE being an unsigned type, causing "i" to be promoted to unsigned int as well. As zero size arrays are a gcc extension, it seems cleanest to add a dummy element with NULL name, and test for it during registration. We'll be able to drop this when we add more CPUs. Cc: Alexander Graf <agraf@suse.de> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Richard Henderson <rth@twiddle.net> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20131223145216.GA22663@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-08arm/xilinx_zynq: Always instantiate the GEMsPeter Crosthwaite1-11/+6
Don't conditionalise GEM instantiation on networking attachments. The device should always be present even if not attached to a network. This allows for probing of the device by expectant guests (such as OS's). This is needed because sysbus (or AXI in Xilinx's real hw case) is not self identifying so the guest has no dynamic way of detecting device absence. Also allows for testing of the GEM in loopback mode with -net none. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 55649779a68ee3ff54b24c339b6fdbdccd1f0ed7.1388800598.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-08target-arm: remove raw_read|write duplicationPeter Crosthwaite1-10/+2
There is an inline duplication of the raw_read and raw_write function bodies. Fix by just calling raw_read/raw_write instead. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: e69281b7e1462b346cb313cf0b89eedc0568125f.1388649290.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-08target-arm: use c13_context field for CONTEXTIDRSergey Fedorov1-1/+1
Use c13_context field instead of c13_fcse for CONTEXTIDR register definition. Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1387521191-15350-1-git-send-email-s.fedorov@samsung.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-08char/cadence_uart: Implement Tx flow controlPeter Crosthwaite1-2/+29
If the UART back-end blocks, buffer in the Tx FIFO to try again later. This stops the IO-thread busy waiting on char back-ends (which causes all sorts of performance problems). Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 4bea048b3ab38425701d82ccc1ab92545c26b79c.1388626249.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-08char/cadence_uart: Delete redundant rx rst logicPeter Crosthwaite1-2/+0
uart_rx_reset() called immediately above already does this. Remove. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 05e30826496cf2579084ed801ac0b2c0d0a3071f.1388626249.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-08char/cadence_uart: Use the TX fifo for transmissionPeter Crosthwaite1-1/+16
Populate the TxFIFO with the Tx data before sending. Prepares support for proper Tx flow control implementation. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: bdf7f8af2ef02839bea18665701bc2612f7baa6f.1388626249.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-08char/cadence_uart: Fix can_receive logicPeter Crosthwaite1-1/+9
The can_receive logic was only taking into account the RxFIFO occupancy. RxFIFO population is only used for the echo and normal modes however. Improve the logic to correctly return the true number of receivable characters based on the current mode: Normal mode: RxFIFO vacancy. Remote loopback: TxFIFO vacancy. Echo mode: The min of the TxFIFO and RxFIFO vacancies. Local Loopback: Return non-zero (to implement droppage) Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 36a58440c9ca5080151e95765c2c81342de8a8df.1388626249.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-08char/cadence_uart: Remove TX timer & add TX FIFO statePeter Crosthwaite1-31/+13
This tx timer implementation is flawed. Despite the controller attempting to time the guest visable assertion of the TX-empty status bit (and corresponding interrupt) the controller is still transmitting characters instantaneously. There is also no sense of multiple character delay. The only side effect of this timer is assertion of tx-empty status. So just remove the timer completely and hold tx-empty as permanently asserted (its reset status). This matches the actual behaviour of instantaneous transmission. While we are VMSD version bumping, add the tx_fifo as device state to prepare for upcomming TxFIFO flow control. Implement the interrupt generation logic for the TxFIFO occupancy. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 7a208a7eb8d79d6429fe28b1396c3104371807b2.1388626249.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-08char/cadence_uart: Define Missing SR/ISR fieldsPeter Crosthwaite1-0/+4
Some (interrupt) status register bits relating to the TxFIFO path were not defined. Define them. This prepares support for proper Tx data path flow control. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 2068b963f0af8cc834c353944e9fa816d950b163.1388626249.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-08char/cadence_uart: Simplify status generationPeter Crosthwaite1-25/+8
The status register bits are always pure functions of other device state. Move the generation of these bits to the update_status() function to simplify. Makes developing much easier as theres now no need to recheck status bits on all the changes to rx/tx fifo state. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 321994929f789096975104f99c55732774be4cae.1388626249.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-08char/cadence_uart: s/r_fifo/rx_fifoPeter Crosthwaite1-4/+4
Rename this field to match the many other uses of "rx". Xilinx docmentation (UG585) also refers to this as "RxFIFO". Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 7386d7cee0ea175f7e53ed5ff045265528d34e32.1388626249.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-08char/cadence_uart: Fix reset.Peter Crosthwaite1-3/+4
Don't reset the uart as an init step. Register the reset function as a proper reset fn instead. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: d82cd2e65e5a6f8b6deeecb6cced61f0bf3f8c89.1388626249.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-08char/cadence_uart: Add missing uart_update_statePeter Crosthwaite1-0/+1
This should be rechecked on bus write accesses as such accesses may change the underlying state that generates the interrupt. Particular relevant for when the guest touches the interrupt status or mask. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1c250cd61b7b8de492fbc8b79b8370958a56d83b.1388626249.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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