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2014-03-05target-ppc: Move To/From VSR InstructionsTom Musta1-0/+59
This patch adds the Move To VSR instructions (mfvsrd, mfvsrwz) and Move From VSR instructions (mtvsrd, mtvsrwa, mtvsrwz). These instructions are unusual in that they are considered a floating point instruction if the indexed VSR is in the first half of the array (0-31) but they are considered vector instructions if the indexed VSR is in the second half of the array (32-63). Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: VSX Stage 4: Add xxleqv, xxlnand and xxlorcTom Musta1-0/+6
This patchs adds the VSX Logical instructions that are new with ISA V2.07: - VSX Logical Equivalence (xxleqv) - VSX Logical NAND (xxlnand) - VSX Logical ORC (xxlorc) Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: VSX Stage 4: Add xscvsxdsp and xscvuxdspTom Musta3-11/+22
This patch adds the VSX Scalar Convert Unsigned Integer Doubleword to Floating Point Format and Round to Single Precision (xscvuxdsp) and VSX Scalar Convert Signed Integer Douglbeword to Floating Point Format and Round to Single Precision (xscvsxdsp) instructions. The existing integer to floating point conversion macro (VSX_CVT_INT_TO_FP) is modified to support the rounding of the intermediate floating point result to single precision. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: VSX Stage 4: Add Scalar SP Fused Multiply-AddsTom Musta3-29/+77
This patch adds the Single Precision VSX Scalar Fused Multiply-Add instructions: xsmaddasp, xsmaddmsp, xssubasp, xssubmsp, xsnmaddasp, xsnmaddmsp, xsnmsubasp, xsnmsubmsp. The existing VSX_MADD() macro is modified to support rounding of the intermediate double precision result to single precision. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: VSX Stage 4: add xsrsqrtespTom Musta3-4/+12
This patch adds the VSX Scalar Reciprocal Square Root Estimate Single Precision (xsrsqrtesp) instruction. The existing VSX_RSQRTE() macro is modified to support rounding of the intermediate double-precision result to single precision. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: VSX Stage 4: Add xssqrtspTom Musta3-4/+12
This patch adds the VSX Scalar Square Root Single Precision (xssqrtsp) instruction. The existing VSX_SQRT() macro is modified to support rounding of the intermediate double-precision result to single-precision. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: VSX Stage 4: Add xsrespTom Musta3-4/+13
This patch adds the VSX Scalar Reciprocal Estimate Single Precision (xsresp) instruction. The existing VSX_RE macro is modified to support rounding of the intermediate double precision result to single precision. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: VSX Stage 4: Add xsdivspTom Musta3-4/+12
This patch adds the VSX Scalar Divide Single Precision (xsdivsp) instruction. The existing VSX_DIV macro is modified to support rounding of the intermediate double precision result to single precision. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: VSX Stage 4: Add xsmulspTom Musta3-4/+12
This patch adds the VSX Scalar Multiply Single-Precision (xsmulsp) instruction. The existing VSX_MUL macro is modified to support rounding of the intermediate result to single precision. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: VSX Stage 4: Add xsaddsp and xssubspTom Musta3-7/+22
This patch adds the VSX Scalar Add Single-Precision (xsaddsp) and VSX Scalar Subtract Single-Precision (xssubsp) instructions. The existing VSX_ADD_SUB macro is modified to support the rounding of the (intermediate) result to single-precision. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: VSX Stage 4: Add stxsiwx and stxsspxTom Musta1-0/+4
This patch adds two store scalar instructions: - Store VSX Scalar as Integer Word Indexed (stxsiwx) - Store VSX Scalar Single-Precision Indexed (stxsspx) Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: VSX Stage 4: Refactor stxsdxTom Musta1-12/+15
This patch refactors the stxsdx instruction. Reusable code is extracted into a macro which will be used in subsequent patches in this series. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: VSX Stage 4: Add lxsiwax, lxsiwzx and lxsspxTom Musta1-0/+14
This patch adds the scalar load instructions introduced in ISA V2.07: - Load VSX Scalar as Integer Word Algebraic Indexd (lxsiwax) - Load VSX Scalar as Integer Word and Zero Indexed (lxsiwzx) - Load VSX Scalar Single-Precision Indexed (lxsspx) Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: VSX Stage 4: Refactor lxsdxTom Musta1-14/+17
This patch refactors the lxsdx generator. Resuable code is isolated into a macro. The macro will be used in subsequent patches in this series to implement other scalar load instructions. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: VSX Stage 4: Add VSX 2.07 FlagTom Musta2-2/+4
This patch adds a flag to identify those VSX instructions that are new to Power ISA V2.07. The flag is added to the Power 8 processor initialization so that the P8 models understand how to decode and emulate instructions in this category. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add VSX Rounding InstructionsTom Musta3-0/+113
This patch adds the VSX Round to Floating Point Integer instructions: - xsrdpi, xsrdpic, xsrdpim, xsrdpip, xsrdpiz - xvrdpi, xvrdpic, xvrdpim, xvrdpip, xvrdpiz - xvrspi, xvrspic, xvrspim, xvrspip, xvrspiz Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add VSX ISA2.06 Integer Conversion InstructionsTom Musta3-0/+173
This patch adds the VSX Integer Conversion instructions defined by V2.06 of the PowerPC ISA: - xscvdpsxds, xscvdpsxws, xscvdpuxds, xscvdpuxws - xvcvdpsxds, xvcvdpsxws, xvcvdpuxds, xvcvdpuxws - xvcvspsxds, xvcvspsxws, xvcvspuxds, xvcvspuxws - xscvsxddp, xscvuxddp - xvcvsxddp, xscvsxwdp, xvcvuxddp, xvcvuxwdp - xvcvsxdsp, xscvsxwsp, xvcvuxdsp, xvcvuxwsp Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add VSX Floating Point to Floating Point Conversion InstructionsTom Musta3-0/+58
This patch adds the VSX instructions that convert between floating point formats: xscvdpsp, xscvspdp, xvcvdpsp, xvcvspdp. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add VSX Vector Compare InstructionsTom Musta3-0/+86
This patch adds the VSX floating point compare vector instructions: - xvcmpeqdp[.], xvcmpgedp[.], xvcmpgtdp[.] - xvcmpeqsp[.], xvcmpgesp[.], xvcmpgtsp[.] Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add VSX xmax/xmin InstructionsTom Musta3-0/+57
This patch adds the VSX floating point maximum and minimum instructions: - xsmaxdp, xvmaxdp, xvmaxsp - xsmindp, xvmindp, xvminsp Because of the Power ISA definitions of maximum and minimum on various boundary cases, the standard softfloat comparison routines (e.g. float64_lt) do not work as well as one might think. Therefore specific routines for comparing 64 and 32 bit floating point numbers are implemented in the PowerPC helper code. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add VSX xscmp*dp InstructionsTom Musta3-0/+45
This patch adds the VSX scalar floating point compare ordered and unordered instructions. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add VSX ISA2.06 Multiply Add InstructionsTom Musta3-0/+172
This patch adds the VSX floating point multiply/add instructions defined by V2.06 of the PowerPC ISA: - xsmaddadp, xvmaddadp, xvmaddasp - xsmaddmdp, xvmaddmdp, xvmaddmsp - xsmsubadp, xvmsubadp, xvmsubasp - xsmsubmdp, xvmsubmdp, xvmsubmsp - xsnmaddadp, xvnmaddadp, xvnmaddasp - xsnmaddmdp, xvnmaddmdp, xvnmaddmsp - xsnmsubadp, xvnmsubadp, xvnmsubasp - xsnmsubmdp, xvnmsubmdp, xvnmsubmsp Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add VSX ISA2.06 xtsqrt InstructionsTom Musta3-0/+63
This patch adds the VSX floating point test for software square root instructions defined by V2.06 of the PowerPC ISA: xstsqrtdp, xvtsqrtdp, xvtsqrtsp. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add VSX ISA2.06 xtdiv InstructionsTom Musta3-0/+76
This patch adds the VSX floating point test for software divide instructions defined by V2.06 of the PowerPC ISA: xstdivdp, xvtdivdp, and xvtdivsp. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add VSX ISA2.06 xrsqrte InstructionsTom Musta3-0/+54
This patch adds the VSX floating point reciprocal square root estimate instructions defined by V2.06 of the PowerPC ISA: xsrsqrtedp, xvrsqrtedp, xvrsqrtesp. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add VSX ISA2.06 xsqrt InstructionsTom Musta3-0/+53
This patch adds the VSX floating point square root instructions defined by V2.06 of the PowerPC ISA: xssqrtdp, xvsqrtdp, xvsqrtsp. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add VSX ISA2.06 xre InstructionsTom Musta3-0/+44
This patch adds the VSX floating point reciprocal estimate instructions defined by V2.06 of the PowerPC ISA: xsredp, xvredp, xvresp. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add VSX ISA2.06 xdiv InstructionsTom Musta3-0/+58
This patch adds the VSX floating point divide instructions defined by V2.06 of the PowerPC ISA: xsdivdp, xvdivdp, xvdivsp. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add VSX ISA2.06 xmul InstructionsTom Musta3-0/+56
This patch adds the VSX floating point multiply instructions defined by V2.06 of the PowerPC ISA: xsmuldp, xvmuldp, xvmulsp. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add VSX ISA2.06 xadd/xsub InstructionsTom Musta3-0/+77
This patch adds the floating point addition and subtraction instructions defined by V2.06 of the PowerPC ISA: xssubdp, xvsubdp and xvsubsp. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: General Support for VSX HelpersTom Musta2-0/+55
This patch adds general support that will be used by the VSX helper routines: - a union describing the various VSR subfields. - access routines to get and set VSRs - VSX decoders - a general routine to generate a handler that invokes a VSX helper. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: Add set_fprf Argument to fload_invalid_op_excp()Tom Musta1-48/+55
The fload_invalid_op_excp() function sets assorted invalid operation status bits. However, it also implicitly modifies the FPRF field of the PowerPC FPSCR. Many VSX instructions set invalid operation bits but do not alter FPRF. Thus the function is more generally useful if the setting of the FPRF field is made conditional via a parameter. All invocations of this routine in existing instructions are modified to pass 1 and thus retain their current behavior. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: disable unsupported modes for SPR_CTRL/SPR_UCTRLAlexey Kardashevskiy1-6/+6
The Figure 17 "SPR encodings" of the PowerISA 2.07 describes CTRL SPR as: priviledged # spr5-9 spr0-4 name mtspr mfspr len cat 136 00100 01000 CTRL - no 32 S 152 00100 11000 CTRL yes - 32 S According to this chart, the hypervisor's CTRL (#152) does not support reading, the user-space's CTRL (UCTRL, #136) does not support writing. This replaces unsupported operations with the default SPR_NOACCESS hook. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05spapr_vscsi: Fix REPORT_LUNS handlingNathan Whitehorn1-0/+60
Intercept REPORT_LUNS commands addressed either to SRP LUN 0 or the well-known LUN for REPORT_LUNS commands. This is required to implement the SAM and SPC specifications. Since SRP implements only a single SCSI target port per connection, the SRP target is required to report all available LUNs in response to a REPORT_LUNS command addressed either to LUN 0 or the well-known LUN. Instead, QEMU was forwarding such requests to the first QEMU SCSI target, with the result that initiators that relied on this feature would only see LUNs on the first QEMU SCSI target. Behavior for REPORT_LUNS commands addressed to any other LUN is not specified by the standard and so is left unchanged. This preserves behavior under Linux and SLOF, which enumerate possible LUNs by hand and so address no commands either to LUN 0 or the well-known REPORT_LUNS LUN. Signed-off-by: Nathan Whitehorn <nwhitehorn@freebsd.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> [agraf: define constant as ULL for 32bit hosts] Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05spapr-pci: enable adding PHB via -deviceAlexey Kardashevskiy1-0/+2
Recent changes introduced cannot_instantiate_with_device_add_yet and removed capability of adding yet another PCI host bridge via command line for SPAPR platform (POWERPC64 server). This brings the capability back and puts SPAPR PHB into "bridge" category. This is not much use for emulated PHB but it is absolutely required for VFIO as we put an IOMMU group onto a separate PHB on SPAPR. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05PPC: KVM: add support for LPCRGreg Kurz1-1/+15
The LPCR special purpose register was introduced with the PowerPC 970MP family. This patch initializes LPCR for the following families: - 970 MP - POWER5+ - POWER7 - POWER8 Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05PPC: KVM: fix "set one register"Alexey Kardashevskiy1-0/+3
Due to missing @one_reg_id assignment in _spr_register(), the kvm_get_one_reg/kvm_set_one_reg API has never really been working. This reenables the API by assigning the @one_reg_id field in the SPR descriptor. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05mmu-hash64: fix Virtual Page Class Key ProtectionCédric Le Goater1-4/+12
commit f80872e21c07edd06eb343eeeefc8af404b518a6 (mmu-hash64: Implement Virtual Page Class Key Protection) added a new page protection mechanism based on page keys and the AMR register to control access. The AMR register allows or prohibits reads and/or writes on a page depending on the control bits associated to the key. A store or a load is only permitted if the associate bit is 0 (Power ISA), and not 1 as the code is currently doing. This patch modifies ppc_hash64_amr_prot() to correct the protection check. This issue was unvailed by commit ccfb53ed6360cac0d5f6f7915ca9ae7eed866412 (target-ppc: fix Authority Mask Register init value) which changed the initialisation value of the AMR register to 0. Signed-off-by: Cédric Le Goater <clg@fr.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: fix Authority Mask Register init valueAlexey Kardashevskiy1-1/+1
The existing default value (-1) of the AMR register forbids data access to all 32 classes. Since the guest linux does not change this register, we end up with the guest hanging right after switching from the real to protected mode. This sets the default AMR value to zero what enables data access for all classes. The only reason for not hitting this bug before is that kvm_arch_put_registers() did not put any SPR to KVM due to missing assignment of @one_reg_id in _spr_register() (which is going to be fixed by a separate patch). Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: dump DAR and DSISRAnton Blanchard1-1/+6
The DAR and DSISR can be very useful when debugging issues, so add them to ppc_cpu_dump_state. We had another bug in this area: all of the v2.06 MMU types were missing. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05kvm: Add a new machine option kvm-typeAneesh Kumar K.V11-15/+53
Targets like ppc64 support different types of KVM, one which use hypervisor mode and the other which doesn't. Add a new machine option kvm-type that helps in selecting the respective ones We also add a new QEMUMachine callback get_vm_type that helps in mapping the string representation of kvm type specified. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> [agraf: spelling fixes, use error_report(), use qemumachine.h] Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05KVM: Split QEMUMachine typedef into separate headerAlexander Graf6-2/+21
Older gcc versions (such as the one in SLES11) get confused when you declare a typedef on the same struct twice. To work around that limitation, let's extract the QEMUMachine typedef into a separate header file that is guarded by preprocessor duplicate include checks. This fixes the following type of compile errors for me: In file included from vl.c:125: include/hw/xen/xen.h:39: error: redefinition of typedef "QEMUMachine" include/sysemu/kvm.h:155: error: previous declaration of "QEMUMachine" was here Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: remove unsupported SPRs from 970 and P5+Alexey Kardashevskiy1-39/+0
SPR_750FX_HID2 and L2CR are not defined in 970* user manuals nor POWER5 bookIV nor PowerISA 2.04, the numbers assigned to them are not defined either so remove them. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: remove embedded MMU SPRs from 970, P5+/7/7+/8Alexey Kardashevskiy1-46/+0
PowerISA 2.04+ puts MMUCFG and MMUCSR0 SPRs to "E" (embedded) category so remove it from POWER7/8 class as it is "S" (server) category. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: fix SPR_CTRL/SPR_UCTRL register numbersAlexey Kardashevskiy1-2/+2
Assuming that "U" in SPR_UCTRL is for "user", there is inconsistency with 970 user manuals/P5-bookIV/PowerISA204 which define the number as: priviledged # spr5-9 spr0-4 name mtspr mfspr len cat 136 00100 01000 CTRL - no 32 S 152 00100 11000 CTRL yes - 32 S This swaps the numbers. No effect from this change is expected though. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: remove powerpc 970gxAlexey Kardashevskiy4-112/+0
The 970GX definition was added in 2007 and it made sense then but this version has never been released to the markets and it does not exist in the real world so there is no point in emulating it. This removes 970GX. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: fix LPCR SPR numberAlexey Kardashevskiy2-2/+2
PowerISA defines LPCR SPR number as 318=0x13E but QEMU uses the value of 316. This fixes the definition of LPCR SPR. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-05target-ppc: fix compile error when PPC_DUMP_CPU is enabledAlexey Kardashevskiy1-2/+3
Since last use of PPC_DUMP_CPU by whoever he/she was, env->tlb became a union and POWERPC CPU class got QOM'ed so defining PPC_DUMP_CPU breaks compile. This fixes compiler errors. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-04block/gluster: Add missing argument to qemu_gluster_init() callAndreas Färber1-1/+1
Commit adccfbcd6020e928db93b2b4faf0dbd05ffbe016 (block: gluster - add reopen support.) did not supply the qemu_gluster_init() Error ** argument, needed since commit a7451cb850d115f257080aff3fbc54f255ebf8f7 (gluster: correctly propagate errors). Pass through qemu_gluster_reopen_prepare()'s errp, as done in qemu_gluster_open(). Cc: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-04Merge remote-tracking branch 'remotes/mjt/tags/trivial-patches-2014-03-04' ↵Peter Maydell12-34/+29
into staging trivial patches for 2014-03-04 # gpg: Signature made Tue 04 Mar 2014 06:13:56 GMT using RSA key ID 74F0C838 # gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" # gpg: aka "Michael Tokarev <mjt@corpit.ru>" # gpg: aka "Michael Tokarev <mjt@debian.org>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D 4324 457C E0A0 8044 65C5 # Subkey fingerprint: E190 8639 3B10 B51B AC2C 8B73 5253 C5AD 74F0 C838 * remotes/mjt/tags/trivial-patches-2014-03-04: vl: Remove unneeded include file qga: Remove unneeded include file qemu-img: Remove unneeded include files exec: Remove unneeded include files util/iov: Use qemu/sockets.h instead of conditional code qjson.h: Remove spurious GCC_FMT_ATTR markup from qobject_from_json() declaration tests/test-int128: Don't use __noclone__ attribute on clang stubs: Optimize dependencies for gdbstub.c tcg: Fix typo in comment (dependancies -> dependencies) bswap: Modify prototypes of st[wl]_{le, be}_p (avoid type conversions) bswap: Modify prototype of stb_p (avoid type conversions) object: Report type in error when not user creatable. include/qemu/host-utils.h: Trivial typo: ctz->cto Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.2.1 (git 2.18.0) at 2024-06-29 02:20:18 +0000