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2013-12-23piix: fix 32bit pci holeGerd Hoffmann3-9/+4
Make the 32bit pci hole start at end of ram, so all possible address space is covered. We used to try and make addresses aligned so they are easier to cover with MTRRs, but since they are cosmetic on KVM, this is probably not worth worrying about. Of course the firmware can use less than that. Leaving space unused is no problem, mapping pci bars outside the hole causes problems though. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-23qdev: switch reset to post-orderPaolo Bonzini4-23/+21
Post-order is the only sensible direction for the reset signals. For example, suppose pre-order is used and the parent has some data structures that cache children state (for example a list of active requests). When the reset method is invoked on the parent, these caches could be in any state. If post-order is used, on the other hand, these will be in a known state when the reset method is invoked on the parent. This change means that it is no longer possible to block the visit of the devices, so the callback is changed to return void. This is not a problem, because PCI was returning 1 exactly in order to achieve the same ordering that this patch implements. PCI can then rely on the qdev core having sent a "reset signal" (whatever that means) to the device, and only do the PCI-specific initialization with pci_do_device_reset. MST: fixed up virtio-ccw Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-23qdev: allow both pre- and post-order vists in qdev walking functionsPaolo Bonzini2-16/+42
Resetting should be done in post-order, not pre-order. However, qdev_walk_children and qbus_walk_children do not allow this. Fix it by adding two extra arguments to the functions. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-23pci: clean up resetting of IRQsPaolo Bonzini1-3/+4
pci_device_reset will deassert the INTX pins, and this will make the irq_count array all-zeroes. Check that this is the case, and remove the existing loop which might even unsync irq_count and irq_state. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-23pci: do not export pci_bus_resetPaolo Bonzini3-8/+3
qbus_reset_all can be used instead. There is no semantic change because pcibus_reset returns 1 and takes care of the device tree traversal. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-23ACPI/DSDT-CPU: cleanup bogus commentIgor Mammedov1-1/+0
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-23ACPI: Q35 DSDT: fix CPU hotplug GPE0.2 handlerIgor Mammedov1-2/+2
Fix bogus CPU hotplug GPE handler. Make Q35 CPU hotplug GPE handler match PIIX4 one, since CPU hotplug event is triggered by GPE0.2 register. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-23acpi: ich9: allow guest to clear SCI rised by GPEIgor Mammedov1-0/+1
it fixes IRQ storm since guest isn't able to lower SCI IRQ after it has been handled when it clears GPE event. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-23acpi: factor out common pm_update_sci() into acpi coreIgor Mammedov4-43/+32
... and rename it into acpi_update_sci() since it changes SCI on only on PM registers status. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-23acpi: piix4: remove not needed GPE0 maskIgor Mammedov1-2/+1
Hardcoded GPE0 mask isn't really needed. Since GPE0_STS initialized with all bits cleared and only QEMU itself can set bits there (i.e. guest can only clear bits in it). So guest can't triger SCI by setting _STS & _EN bits and there is not reason to mask out not supported _STS bits since they shouldn't be set by QEMU in the first place. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-23i440fx-test: verify firmware under 4G and 1M, both -bios and -pflashLaszlo Ersek1-6/+75
Check whether the firmware is not hidden by other memory regions. Qemu is started in paused mode: it shouldn't try to interpret generated garbage. Signed-off-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-23i440fx-test: generate temporary firmware blobLaszlo Ersek1-0/+60
The blob is 64K in size and contains 0x00..0xFF repeatedly. The client code added to main() wouldn't make much sense in the long term. It helps with debugging and it silences gcc about create_blob_file() being unused, and we'll replace it in the next patch anyway. Signed-off-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-23i440fx-test: give each GTest case its own qtestLaszlo Ersek1-13/+19
The current two GTest cases, /i440fx/defaults and /i440fx/pam can share a qemu process, but the next two cases will need dedicated instances. It is messy (and order-dependent) to dynamically configure GTest cases one by one to start, stop, or keep the current qtest (*); let's just have each GTest work with its own qtest. The performance difference should be negligible. (*) As g_test_run() can be invoked at most once per process startup, and it runs GTest cases in sequence, we'd need clumsy data structures to control each GTest case to start/stop/keep the qemu instance. Or, we'd have to code the same information into the test methods themselves, which would make them even more order-dependent. Signed-off-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-23i440fx-test: qtest_start() should be paired with qtest_end()Laszlo Ersek1-6/+4
Similarly to commit 1d9358e6 ("libqtest: New qtest_end() to go with qtest_start()"). Signed-off-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-23hw/i386/pc_sysfw: support two flash drivesLaszlo Ersek1-19/+86
This patch allows the user to usefully specify -drive file=img_1,if=pflash,format=raw,readonly \ -drive file=img_2,if=pflash,format=raw on the command line. The flash images will be mapped under 4G in their reverse unit order -- that is, with their base addresses progressing downwards, in increasing unit order. (The unit number increases with command line order if not explicitly specified.) This accommodates the following use case: suppose that OVMF is split in two parts, a writeable host file for non-volatile variable storage, and a read-only part for bootstrap and decompressible executable code. The binary code part would be read-only, centrally managed on the host system, and passed in as unit 0. The variable store would be writeable, VM-specific, and passed in as unit 1. 00000000ffe00000-00000000ffe1ffff (prio 0, R-): system.flash1 00000000ffe20000-00000000ffffffff (prio 0, R-): system.flash0 (If the guest tries to write to the flash range that is backed by the read-only drive, pflash_update() is never called; various flash programming/erase errors are returned to the guest instead. See the callers of pflash_update(), and the initialization of "pfl->ro", in "hw/block/pflash_cfi01.c".) Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-23pc_piix: document gigabyte_alignMichael S. Tsirkin1-0/+11
Document the logic behind the below/above 4G split. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-23piix: gigabyte alignment for ramGerd Hoffmann1-2/+5
Map 3G (i440fx) of memory below 4G, so the RAM pieces are nicely aligned to gigabyte borders. Keep old memory layout for (a) old machine types and (b) in case all memory fits below 4G and thus we don't have to split RAM into pieces in the first place. The later makes sure this change doesn't take away memory from 32bit guests. So, with i440fx and up to 3.5 GB of memory, all of it will be mapped below 4G. With more than 3.5 GB of memory 3 GB will be mapped below 4G and the remaining amount will be mapped above 4G. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-22PPC: Fix compilation with TCG debugAlexander Graf1-62/+81
The recent VSX patches broken compilation of QEMU when configurated with --enable-debug, as it was treating "target long" TCG variables as "i64" which is not true for 32bit targets. This patch fixes all the places that the compiler has found to use the correct variable type and if necessary manually cast. Reported-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-12-21Merge tag 'signed-s390-for-upstream' of git://github.com/agraf/qemuAurelien Jarno3-52/+50
Patch queue for s390 - 2013-12-18 This covers mostly minor bug fixes and implements the SIGP START hypercall which allows to start a remote CPU without changing its state. Cornelia Huck (1): s390x/kvm: Fix diagnose handling. Thomas Huth (7): s390x/kvm: Removed duplicated SIGP defines s390x/kvm: Removed s390_store_status stub s390x/kvm: Fix coding style in handle_sigp() s390x/kvm: Implemented SIGP START s390x/kvm: Simplified the calculation of the SIGP order code s390x/kvm: Fixed condition code for unknown SIGP orders s390x/ioinst: CHSC has to set a condition code * tag 'signed-s390-for-upstream' of git://github.com/agraf/qemu: s390x/ioinst: CHSC has to set a condition code s390x/kvm: Fixed condition code for unknown SIGP orders s390x/kvm: Simplified the calculation of the SIGP order code s390x/kvm: Implemented SIGP START s390x/kvm: Fix coding style in handle_sigp() s390x/kvm: Removed s390_store_status stub s390x/kvm: Removed duplicated SIGP defines s390x/kvm: Fix diagnose handling.
2013-12-21target-sh4: Use new qemu_ld/st opcodesAurelien Jarno1-77/+90
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-12-21target-mips: Use new qemu_ld/st opcodesAurelien Jarno1-67/+52
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-12-21tcg/i386: fix a commentAurelien Jarno1-1/+1
The comments apply to 8-bit stores, not 8-byte stores. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-12-19Merge remote-tracking branch 'agraf/tags/signed-ppc-for-upstream' into stagingAnthony Liguori33-387/+1237
Patch queue for ppc - 2013-12-20 Alexander Graf (3): PPC: Use default pci bus name for grackle and heathrow roms: Flush icache when writing roms to guest memory PPC: Add VSX to hflags Alexey Kardashevskiy (5): powerpc: add PVR mask support target-ppc: move POWER7+ to a separate family spapr-rtas: replace return code constants with macros spapr-rtas: add ibm, (get|set)-system-parameter spapr: make sure RMA is in first mode of first memory node Greg Kurz (1): target-ppc: add stubs for KVM breakpoints Paolo Bonzini (1): spapr: tie spapr-nvram to -pflash Paul Mackerras (1): spapr: limit numa memory regions by ram size Peter Crosthwaite (2): device_tree: s/qemu_devtree/qemu_fdt globally device_tree: qemu_fdt_setprop: Rename val_array arg Tom Musta (19): Declare and Enable VSX Add MSR VSX and Associated Exception Add VSX Instruction Decoders Add VSR to Global Registers Add lxvd2x Add stxvd2x Add xxpermdi Add lxsdx Add lxvdsx Add lxvw4x Add stxsdx Add stxvw4x Add VSX Scalar Move Instructions Add VSX Vector Move Instructions Add Power7 VSX Logical Instructions Add xxmrgh/xxmrgl Add xxsel Add xxspltw Add xxsldwi * agraf/tags/signed-ppc-for-upstream: (32 commits) spapr: limit numa memory regions by ram size spapr: make sure RMA is in first mode of first memory node device_tree: qemu_fdt_setprop: Rename val_array arg device_tree: s/qemu_devtree/qemu_fdt globally PPC: Add VSX to hflags Add xxsldwi Add xxspltw Add xxsel Add xxmrgh/xxmrgl Add Power7 VSX Logical Instructions Add VSX Vector Move Instructions Add VSX Scalar Move Instructions roms: Flush icache when writing roms to guest memory spapr: tie spapr-nvram to -pflash PPC: Use default pci bus name for grackle and heathrow spapr-rtas: add ibm, (get|set)-system-parameter spapr-rtas: replace return code constants with macros target-ppc: move POWER7+ to a separate family Add stxvw4x Add stxsdx ...
2013-12-20spapr: limit numa memory regions by ram sizePaul Mackerras1-4/+16
This makes sure that all NUMA memory blocks reside within RAM or have zero length. Reviewed-by: Thomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20spapr: make sure RMA is in first mode of first memory nodeAlexey Kardashevskiy1-6/+11
The SPAPR specification says that the RMA starts at the LPAR's logical address 0 and is the first logical memory block reported in the LPAR’s device tree. So SLOF only maps the first block and that block needs to span the full RMA. This makes sure that the RMA area is where SLOF expects it. Reviewed-by: Thomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20device_tree: qemu_fdt_setprop: Rename val_array argPeter Crosthwaite2-3/+3
Looking at the implementation, this doesn't really have a lot to do with arrays. Its just a pointer to a buffer and is passed through to the wrapped fn (qemu_fdt_setprop) unchanged. So rename to make it consistent with libfdt, which in the wrapped function just calls it "val". Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20device_tree: s/qemu_devtree/qemu_fdt globallyPeter Crosthwaite12-284/+285
The qemu_devtree API is a wrapper around the fdt_ set of APIs. Rename accordingly. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> [agraf: also convert hw/arm/virt.c] Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20PPC: Add VSX to hflagsAlexander Graf1-1/+1
We generate different code depending on whether MSR_VSX is set or clear, so it needs to be part of our hflags too which indicate whether we're still in the same translation block cache bucket. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add xxsldwiTom Musta1-0/+62
This patch adds the VSX Shift Left Double by Word Immediate (xxsldwi) instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add xxspltwTom Musta1-0/+31
This patch adds the VSX Splat Word (xxsplatw) instruction. This is the first instruction to use the UIM immediate field and consequently a decoder is also added. V2: reworked implementation per Richard Henderson's comments. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add xxselTom Musta1-0/+76
This patch adds the VSX Select (xxsel) instruction. The xxsel instruction has four VSR operands. Thus the xC instruction decoder is added. The xxsel instruction is massively overloaded in the opcode table since only bits 26 and 27 are opcode bits. This overloading is done in matrix fashion with two macros (GEN_XXSEL_ROW and GEN_XX_SEL). V2: (1) eliminated unecessary XXSEL macro (2) tighter implementation using tcg_gen_andc_i64. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add xxmrgh/xxmrglTom Musta1-0/+41
This patch adds the VSX Merge High Word and VSX Merge Low Word instructions. V2: Now implemented using deposit (per Richard Henderson's comment) Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add Power7 VSX Logical InstructionsTom Musta1-0/+29
This patch adds the VSX logical instructions that are defined by the Version 2.06 Power ISA (aka Power7): - xxland - xxlandc - xxlor - xxlxor - xxlnor Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add VSX Vector Move InstructionsTom Musta1-0/+71
This patch adds the vector move instructions: - xvabsdp - Vector Absolute Value Double-Precision - xvnabsdp - Vector Negative Absolute Value Double-Precision - xvnegdp - Vector Negate Double-Precision - xvcpsgndp - Vector Copy Sign Double-Precision - xvabssp - Vector Absolute Value Single-Precision - xvnabssp - Vector Negative Absolute Value Single-Precision - xvnegsp - Vector Negate Single-Precision - xvcpsgnsp - Vector Copy Sign Single-Precision V3: Per Paolo Bonzini's suggestion, used a temporary for the sign mask and andc. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add VSX Scalar Move InstructionsTom Musta1-0/+70
This patch adds the VSX scalar move instructions: - xsabsdp (Scalar Absolute Value Double-Precision) - xsnabspd (Scalar Negative Absolute Value Double-Precision) - xsnegdp (Scalar Negate Double-Precision) - xscpsgndp (Scalar Copy Sign Double-Precision) A common generator macro (VSX_SCALAR_MOVE) is added since these instructions vary only slightly from each other. Macros to support VSX XX2 and XX3 form opcodes are also added. These macros handle the overloading of "opcode 2" space (instruction bits 26:30) caused by AX and BX bits (29 and 30, respectively). V3: Per feedback from Paolo Bonzini, moved the sign mask into a temporary and used andc. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20roms: Flush icache when writing roms to guest memoryAlexander Graf3-5/+47
We use the rom infrastructure to write firmware and/or initial kernel blobs into guest address space. So we're basically emulating the cache off phase on very early system bootup. That phase is usually responsible for clearing the instruction cache for anything it writes into cachable memory, to ensure that after reboot we don't happen to execute stale bits from the instruction cache. So we need to invalidate the icache every time we write a rom into guest address space. We do not need to do this for every DMA since the guest expects it has to flush the icache manually in that case. This fixes random reboot issues on e5500 (booke ppc) for me. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20spapr: tie spapr-nvram to -pflashPaolo Bonzini1-11/+3
spapr-nvram's drive property is currently connected to a non-existent "-machine nvram=<drivename>" option. Instead, tie it to -pflash like other non-volatile RAM devices. This provides the following possibilities for adding a backend for the sPAPR non-volatile RAM: * -pflash filename * -drive if=pflash,file=filename,format=raw,... * -drive if=none,file=filename,format=raw,id=foo,... -global spapr-nvram.drive=foo Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20PPC: Use default pci bus name for grackle and heathrowAlexander Graf2-3/+3
There's no good reason to call our bus "pci" rather than let the default bus name take over ("pci.0"). The big downside to calling it different from anyone else is that tools that pass -device get confused. They are looking for a bus "pci.0" rather than "pci". To make life easier for everyone, let's just drop the name override. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20spapr-rtas: add ibm, (get|set)-system-parameterAlexey Kardashevskiy2-0/+49
This adds very basic handlers for ibm,get-system-parameter and ibm,set-system-parameter RTAS calls. The only parameter handled at the moment is "platform-processor-diagnostics-run-mode" which is always disabled and does not support changing. This is expected to make "ppc64_cpu --run-mode=1" happy. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> [agraf: s/papameter/parameter/g] Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20spapr-rtas: replace return code constants with macrosAlexey Kardashevskiy7-67/+74
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20target-ppc: move POWER7+ to a separate familyAlexey Kardashevskiy3-1/+41
So far POWER7+ was a part of POWER7 family. However it has a different PVR base value so in order to support PVR masks, it needs a separate family class. This adds a new family class, PVR base and mask values and moves Power7+ v2.1 CPU to a new family. The class init function is copied from the POWER7 family. This defines a firmware name for the new family as "PowerPC,POWER7+" instead of previously used "PowerPC,POWER7" from the POWER7 family. The reason for that is that the Sapphire firmware (a h0st firmware) uses "PowerPC,POWER7+" already and since no specification defines exactly the CPU nodes naming in the device tree, we better stay in sync with the host firmware. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add stxvw4xTom Musta1-0/+28
This patch adds the Store VSX Vector Word*4 Indexed (stxvw4x) instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add stxsdxTom Musta1-0/+15
This patch adds the Store VSX Scalar Doubleword Indexed (stxsdx) instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add lxvw4xTom Musta1-0/+29
This patch adds the Load VSX Vector Word*4 Indexed (lxvw4x) instruction. V2: changed to use deposit_i64 per Richard Henderson's review. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add lxvdsxTom Musta1-0/+16
This patch adds the Load VSX Vector Doubleword & Splat Indexed (lxvdsx) instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add lxsdxTom Musta1-0/+16
This patch adds the Load VSX Scalar Doubleowrd Indexed (lxsdx) instruction. The lower 8 bytes of the target register are undefined; this implementation leaves those bytes unaltered. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add xxpermdiTom Musta1-1/+40
This patch adds the xxpermdi instruction. The instruction uses bits 22, 23, 29 and 30 for non-opcode fields (DM, AX and BX). This results in overloading of the opcode table with aliases, which can be seen in the GEN_XX3FORM_DM macro. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add stxvd2xTom Musta1-0/+18
This patch adds the stxvd2x instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add lxvd2xTom Musta1-0/+18
This patch adds the lxvd2x instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20Add VSR to Global RegistersTom Musta1-0/+27
This patch adds VSX VSRs to the the list of global register indices. More specifically, it adds the lower halves of the first 32 VSRs to the list of global register indices. The upper halves of the first 32 VSRs are already defined via cpu_fpr[]. And the second 32 VSRs are already defined via the cpu_avrh[] and cpu_avrl[] arrays. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
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