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2012-06-21qemu-ga: add guest-fstrim commandPaolo Bonzini3-3/+106
FITRIM is a mounted filesystem feature to discard (or "trim") blocks which are not in use by the filesystem. This is useful for solid-state drives (SSDs) and thinly-provisioned storage. Provide access to the feature from the host so that filesystems can be trimmed periodically or before migration. Here is an example using scsi_debug: # modprobe scsi_debug lbpu=1 lbpws=1 # sg_vpd -p0xb2 /dev/sdb Logical block provisioning VPD page (SBC): Unmap command supported (LBPU): 1 Write same (16) with unmap bit supported (LBWS): 1 Write same (10) with unmap bit supported (LBWS10): 0 # mke2fs /dev/sdb # cat /sys/bus/pseudo/drivers/scsi_debug/map 1-616,16257-16383 # mount /dev/sdb /run/media/pbonzini/test # dd if=/dev/zero of=/run/media/pbonzini/test/file # cat map 1-616,645-1588,1599-4026,4029-16383 # rm /run/media/pbonzini/test/file # ./qemu-ga /dev/fd/0 {"execute":"guest-fstrim"} {"return": {}} # cat map 1-612 Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Luiz Capitulino <lcapitulino@redhat.com> Reviewed-by: Michal Privoznik <mprivozn@redhat.com> Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
2012-06-21qemu-ga: make names more generic for mount list functionsPaolo Bonzini1-18/+18
We will use these functions and types for more than FSFREEZE, so rename them. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Luiz Capitulino <lcapitulino@redhat.com> Reviewed-by: Michal Privoznik <mprivozn@redhat.com> Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
2012-06-21libcacard: build fixesBlue Swirl2-6/+7
Link trace objects to fix these errors: LINK vscclient oslib-posix.o: In function `trace_qemu_vfree': /src/qemu/obj-amd64/./trace.h:39: undefined reference to `trace1' oslib-posix.o: In function `trace_qemu_memalign': /src/qemu/obj-amd64/./trace.h:31: undefined reference to `trace3' oslib-posix.o: In function `trace_qemu_vmalloc': /src/qemu/obj-amd64/./trace.h:35: undefined reference to `trace2' Add LDFLAGS to vscclient link command. Clean up also in subdirectories of libcacard. Use quiet-command for sed invocation. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Acked-by: Alon Levy <alevy@redhat.com>
2012-06-21qtest: add a fuzz test to fdc-testBlue Swirl1-0/+17
Add a simple register fuzzing test to floppy controller tests. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-21fdc: use LOG_UNIMP loggingBlue Swirl1-13/+17
Convert uses of FLOPPY_ERROR to either FLOPPY_DPRINTF (for implemented cases) or to use LOG_UNIMP (unimplemented). Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-21qemu-log: use LOG_UNIMP for some target CPU casesBlue Swirl5-38/+58
Use LOG_UNIMP for some target CPU cases. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Acked-by: Alexander Graf <agraf@suse.de>
2012-06-21qemu-log: add log category for unimplemented functionalityBlue Swirl2-0/+3
Add new log category (LOG_UNIMP) for unimplemented functionality. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-21qemu-log: cleanupBlue Swirl8-113/+168
Don't use global variables directly but via accessor functions. Rename globals. Convert macros to functions, add GCC format attributes. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-21qemu-log: move logging to qemu-log.cBlue Swirl5-151/+170
Move logging functions from exec.c to qemu-log.c, compile it only once. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-21Introduce Xen PCI Passthrough, MSIJiang Yunhong5-2/+1173
A more complete history can be found here: git://xenbits.xensource.com/qemu-xen-unstable.git Signed-off-by: Jiang Yunhong <yunhong.jiang@intel.com> Signed-off-by: Shan Haitao <haitao.shan@intel.com> Signed-off-by: Anthony PERARD <anthony.perard@citrix.com> Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
2012-06-21Introduce apic-msidef.hAnthony PERARD2-10/+31
This patch move the msi definition from apic.c to apic-msidef.h. So it can be used also by other .c files. Signed-off-by: Anthony PERARD <anthony.perard@citrix.com> Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Acked-by: Michael S. Tsirkin <mst@redhat.com>
2012-06-21Introduce Xen PCI Passthrough, PCI config space helpersAllen Kay3-0/+1399
A more complete history can be found here: git://xenbits.xensource.com/qemu-xen-unstable.git Signed-off-by: Allen Kay <allen.m.kay@intel.com> Signed-off-by: Guy Zana <guy@neocleus.com> Signed-off-by: Anthony PERARD <anthony.perard@citrix.com> Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
2012-06-21Introduce Xen PCI Passthrough, qdeviceAllen Kay6-0/+1087
A more complete history can be found here: git://xenbits.xensource.com/qemu-xen-unstable.git Signed-off-by: Allen Kay <allen.m.kay@intel.com> Signed-off-by: Guy Zana <guy@neocleus.com> Signed-off-by: Anthony PERARD <anthony.perard@citrix.com> Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
2012-06-21qdev-properties: Introduce pci-host-devaddr.Anthony PERARD3-0/+117
This new property will be used to specify a host pci device address. Signed-off-by: Anthony PERARD <anthony.perard@citrix.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
2012-06-21pci.c: Add opaque argument to pci_for_each_device.Anthony PERARD3-9/+14
The purpose is to have a more generic pci_for_each_device by passing an extra argument to the function called on every device. This patch will be used in a next patch. Signed-off-by: Anthony PERARD <anthony.perard@citrix.com> Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
2012-06-21Introduce XenHostPCIDevice to access a pci device on the host.Anthony PERARD3-0/+452
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com> Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
2012-06-21configure: Introduce --enable-xen-pci-passthrough.Anthony PERARD1-0/+29
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com> Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
2012-06-21pci_ids: Add INTEL_82599_SFP_VF id.Anthony PERARD1-0/+1
We are using this in our quirk lookup provided by patch titled: Introduce Xen PCI Passthrough, PCI config space helpers. Signed-off-by: Anthony PERARD <anthony.perard@citrix.com> Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
2012-06-21xilinx_timer: Fixed deadlock issuePeter A. G. Crosthwaite1-1/+1
The timer was deadlocking when the interval was set too low. It would cause a flood of timer events and the CPU would halt indefinately. This is a known issue and theres a generic workaround in place in ptimer on ptimer_set_limit(), however the Xilinx timer uses ptimer_set_count() instead of set_limit. Changed the call to set_count() to an equivalent call of set_limit() instead, which brings the workaround into play. Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2012-06-21xilinx_timer: Removed include of qemu-timerPeter A. G. Crosthwaite1-1/+0
The Xilinx timer does not interact with the qemu_timer API, so dont include it. Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2012-06-21xenstore: Use <xenstore.h>Anthony PERARD2-2/+6
In the next release of Xen (4.2), xs.h became deprecated. Signed-off-by: Anthony PERARD <anthony.perard@citrix.com> Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
2012-06-21xen: Reorganize includes of Xen headers.Anthony PERARD5-25/+12
Because xs.h will be remove in future release of Xen, this patch removes the extra includes of this headers. Also, it removes the extra includes of xenctrl.h and xen/io/xenbus.h as there already are in xen_common.h. Signed-off-by: Anthony PERARD <anthony.perard@citrix.com> Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
2012-06-20uhci: fix uhci_async_cancel_allGerd Hoffmann1-2/+2
We update the QTAILQ in the loop, thus we must use the SAFE version to make sure we don't touch the queue struct after freeing it. https://bugzilla.novell.com/show_bug.cgi?id=766310 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2012-06-20usb-host: live migration supportGerd Hoffmann1-1/+46
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2012-06-20usb-host: attach only to running guestGerd Hoffmann1-15/+17
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2012-06-20ehci: tracing improvementsGerd Hoffmann2-4/+8
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2012-06-20usb: restore USBDevice->attached on vmloadGerd Hoffmann1-0/+13
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2012-06-20ehci: add live migration supportGerd Hoffmann1-6/+56
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2012-06-20target-arm: Remove ARM_CPUID_* macrosPeter Maydell3-56/+26
All the uses of ARM_CPUID() to vary behaviour have now been removed, so we can delete the ARM_CPUID_* macros now. The one exception is the TI915T/925T, because of its odd behaviour where the MIDR value can be changed at runtime. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de>
2012-06-20target-arm: Remove remaining old cp15 infrastructurePeter Maydell3-100/+1
There are now no uses of the old cp15 infrastructure, so it can be deleted. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Move block cache ops to new cp15 frameworkPeter Maydell2-6/+14
Move the v6 optional block cache ops to the new cp15 framework. This includes only providing them on the CPUs which implemented them, rather than the previous blunderbuss approach of making all MCRR instructions on all CPUs act as NOPs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Remove c0_cachetype CPUARMState fieldPeter Maydell2-4/+1
Remove the no-longer-used CPUARMState c0_cachetype field. Although this was a constant register we had it in our migration state. Drop this (with resulting version bump) because for ARM currently we prefer cleaner migration code and have not stabilised migration format yet. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert final ID registersPeter Maydell2-50/+68
Convert the final ID registers to the new cp15 scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert MPIDRPeter Maydell3-22/+31
Convert the MPIDR to the new cp15 register scheme. This includes giving it its own feature bit rather than doing a CPUID value check. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 cache ID registersPeter Maydell3-32/+33
Convert the cp15 cache ID registers to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 crn=0 crm={1,2} feature registersPeter Maydell3-24/+54
Convert the cp15 crn=0 crm={1,2} features registers to the new cp reg framework. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 crn=1 registersPeter Maydell3-76/+61
Convert the cp15 crn=1 registers to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 crn=9 registersPeter Maydell2-79/+59
Convert cp15 crn=9 registers (mostly cache lockdown) to the new scheme. Note that this change makes OMAPCP cores RAZ/WI the whole c9 space. This is a change from previous behaviour, but a return to the behaviour of commit c3d2689d when OMAP1 support was first added -- subsequent commits have clearly accidentally relegated the OMAPCP RAZ condition to only a subset of the crn=9 space when adding support for other cores. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 crn=6 registersPeter Maydell2-53/+45
Convert the cp15 crn=6 registers to the new scheme. Note that this includes some minor tidyup: drop an unnecessary underdecoding of op2 on OMAPCP cores, and only implement the pre-v6 c6,c0,0,1 IFAR on the 1026 and not on the other ARMv5 cores, which didn't have it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: convert cp15 crn=7 registersPeter Maydell3-11/+74
Convert the cp15 crn=7 registers to the new scheme. Note that to do this we have to distinguish some registers used on the ARM9 and ARM10 from some which are ARM1176 only. This is because the old code returned a value of 0 but always set the Z flag (by clearing env->ZF, since we store the Z flag in CPUState inverted). This is inconsistent with actual ARM CPU behaviour, which only sets flags for reads to r15 and sets them based on the top bits of the result. However it happened to work for the two common use cases for cp15 crn=7 reads: * On ARM9 and ARM10 the cache clean-and-test operations are typically done with a destination of r15 so that you can do a "loop: mrc ... ; bne loop" to keep cleaning until the cache is finally clean; always setting the Z flag means this loop terminates immediately * on ARM1176 the Cache Dirty Status Register reads as zero if the cache is dirty; returning 0 means this is correctly implemented for QEMU Since the new coprocessor register framework does the right thing of always setting flags based on the returned result for reads to r15, we need to split these up so that we can return (1<<30) for the ARM9/ARM10 registers but 0 for the ARM1176 one. This allows us to remove the nasty hack which always sets Z. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 VA-PA translation registersPeter Maydell1-43/+65
Convert the cp15 VA-PA translation registers (a subset of the crn=7 regs) to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 MMU TLB controlPeter Maydell1-20/+43
Convert cp15 MMU TLB control (crn=8) to new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 crn=15 registersPeter Maydell3-117/+126
Convert the cp15 crn=15 (implementation specific) registers to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 crn=10 registersPeter Maydell1-6/+5
We RAZ/WI the entire block of crn=10 registers. Note that this actually covers not just the implementation-defined TLB lockdown registers but also a number of v7 VMSA memory attribute registers which we would need to implement to support TEX remap. We retain the previous QEMU behaviour in this conversion, though. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 crn=13 registersPeter Maydell1-30/+31
Convert the cp15 crn=13 registers (FCSEIDR, CONTEXTIDR, and the ARM946 Trace Process Identifier Register). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 crn=2 registersPeter Maydell2-56/+33
Convert the cp15 crn=2 registers (MMU page table control, MPU cache control) to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert MMU fault status cp15 registersPeter Maydell1-81/+107
Convert the MMU fault status and MPU access permission cp15 registers to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert cp15 c3 registerPeter Maydell1-6/+12
Convert the cp15 c3 register (MMU domain access control or MPU write buffer control). NB that this is horribly underdecoded for modern cores (should be crn=3,crm=0, opc1=0,opc2=0) but this change preserves the existing QEMU behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert generic timer cp15 regsPeter Maydell1-12/+11
Convert the (dummy) generic timer cp15 implementation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert performance monitor registersPeter Maydell3-149/+158
Convert the v7 performance monitor cp15 registers to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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