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2012-06-24qemu-log: Add GCC format attributeStefan Weil1-1/+2
The new inline function qemu_log_vprintf should use this attribute. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-24Merge branch 'ppc-for-upstream' of git://repo.or.cz/qemu/agrafBlue Swirl35-8463/+9858
* 'ppc-for-upstream' of git://repo.or.cz/qemu/agraf: (72 commits) PPC: BookE206: Bump MAS2 to 64bit PPC: BookE: Support 32 and 64 bit wide MAS2 PPC: Extract SPR dump generation into its own function PPC: Add e5500 CPU target PPC: BookE: Make ivpr selectable by CPU type PPC: BookE: Implement EPR SPR PPC: Add support for MSR_CM PPC: Add some booke SPR defines uImage: increase the gzip load size PPC: e500: allow users to set the /compatible property via -machine dt: make setprop argument static PPC: e500: Refactor serial dt generation dt: Add global option to set phandle start offset PPC: e500: Extend address/size of / to 64bit PPC: e500: Define addresses as always 64bit PPC: e500: Use new SOC dt format PPC: e500: Use new MPIC dt format Revert "dt: temporarily disable subtree creation failure check" PPC: e500: enable manual loading of dtb blob PPC: e500: dt: use target_phys_addr_t for ramsize ...
2012-06-24Merge branch 'target-arm.for-upstream' of ↵Blue Swirl11-1536/+1889
git://git.linaro.org/people/pmaydell/qemu-arm * 'target-arm.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm: (33 commits) target-arm: Remove ARM_CPUID_* macros target-arm: Remove remaining old cp15 infrastructure target-arm: Move block cache ops to new cp15 framework target-arm: Remove c0_cachetype CPUARMState field target-arm: Convert final ID registers target-arm: Convert MPIDR target-arm: Convert cp15 cache ID registers target-arm: Convert cp15 crn=0 crm={1,2} feature registers target-arm: Convert cp15 crn=1 registers target-arm: Convert cp15 crn=9 registers target-arm: Convert cp15 crn=6 registers target-arm: convert cp15 crn=7 registers target-arm: Convert cp15 VA-PA translation registers target-arm: Convert cp15 MMU TLB control target-arm: Convert cp15 crn=15 registers target-arm: Convert cp15 crn=10 registers target-arm: Convert cp15 crn=13 registers target-arm: Convert cp15 crn=2 registers target-arm: Convert MMU fault status cp15 registers target-arm: Convert cp15 c3 register ...
2012-06-24Merge branch 's390-for-upstream' of git://repo.or.cz/qemu/agrafBlue Swirl5-8/+52
* 's390-for-upstream' of git://repo.or.cz/qemu/agraf: s390: stop target cpu on sigp initial reset s390: make kvm_stat work on s390 kvm: Update kernel headers s390x: fix s390 virtio aliases
2012-06-24Merge branch 'arm-devs.for-upstream' of ↵Blue Swirl16-487/+569
git://git.linaro.org/people/pmaydell/qemu-arm * 'arm-devs.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm: arm_boot: Conditionalised DTB command line update cadence_ttc: changed master clock frequency cadence_gem: avoid stack-writing buffer-overrun hw/a9mpcore: Fix compilation failure if physaddrs are 64 bit hw/omap.h: Drop broken MEM_VERBOSE tracing hw/armv7m_nvic: Make the NVIC a freestanding class hw/arm_gic: Move CPU interface memory region setup into arm_gic_init hw/arm_gic.c: Make NVIC interrupt numbering a runtime setting hw/arm_gic: Make CPU target registers RAZ/WI on uniprocessor hw/arm_gic: Add qdev property for GIC revision hw/armv7m_nvic: Use MemoryRegions for NVIC specific registers hw/arm_gic: Move NVIC specific reset to armv7m_nvic_reset hw/arm_gic: Remove the special casing of NCPU for the NVIC hw/arm_gic: Remove NVIC ifdefs from gic_state struct arm_boot: Fix typos in comment ARM: Exynos4210 IRQ: Introduce new IRQ gate functionality.
2012-06-24PPC: BookE206: Bump MAS2 to 64bitAlexander Graf1-1/+1
On 64bit capable systems, MAS2 can actually hold a 64bit virtual page address. So increase the mask for its EPN. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: BookE: Support 32 and 64 bit wide MAS2Alexander Graf1-1/+18
The MAS registers on BookE are all 32 bit wide, except for MAS2, which can hold up to 64 bit on 64 bit capable CPUs. Reflect this in the SPR setting code, so that the guest can never write invalid values in them. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: Extract SPR dump generation into its own functionAlexander Graf1-12/+18
This patch moves the debug #ifdef'ed SPR trace generation into its own function, so we can call it from multiple places. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: Add e5500 CPU targetAlexander Graf1-3/+93
This patch adds e5500's CPU initialization to the TCG CPU initialization code. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: BookE: Make ivpr selectable by CPU typeAlexander Graf1-4/+5
IVPR can either hold 32 or 64 bit addresses, depending on the CPU type. Let the CPU initialization function pass in its mask itself, so we can easily extend it. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: BookE: Implement EPR SPRAlexander Graf5-0/+39
On the e500 series, accessing SPR_EPR magically turns into an access at that CPU's IACK register on the MPIC. Implement that logic to get kernels that make use of that feature work. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: Add support for MSR_CMAlexander Graf4-6/+16
The BookE variant of MSR_SF is MSR_CM. Implement everything it takes in TCG to support running 64bit code with MSR_CM set. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: Add some booke SPR definesAlexander Graf1-0/+22
The number of SPRs avaiable in different PowerPC chip is still increasing. Add definitions for the MAS7_MAS3 SPR and all currently known bits in EPCR. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24uImage: increase the gzip load sizeAlexander Graf1-2/+2
Recent u-boot has different defines for its gzip extract buffer, but the common ground seems to be 64MB. So let's bump it up to that, enabling me to load my test image again ;). Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: e500: allow users to set the /compatible property via -machineAlexander Graf2-3/+13
Device trees usually have a node /compatible, which indicate which machine type we're looking at. For quick prototyping, it can be very useful to change the contents of that node via the command line. Thus, introduce a new option to -machine called dt_compatible, which when set changes the /compatible contents to its value. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24dt: make setprop argument staticAlexander Graf2-2/+2
Whatever we pass in to qemu_devtree_setprop to put into the device tree will not get modified by that function, so it can easily be declared const. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@petalogix.com>
2012-06-24PPC: e500: Refactor serial dt generationAlexander Graf1-28/+26
When generating serial port device tree nodes, we duplicate quite a bit of code, because there are 2 of them in the mpc8544ds board we emulate. Shove the generating code into a function, so we duplicate less code. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24dt: Add global option to set phandle start offsetAlexander Graf2-1/+31
If anyone outside of QEMU wants to mess with a QEMU generated device tree, he needs to know which range phandles are valid in. So let's expose a machine option that an external program can use to set the start allocate id for phandles in QEMU. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: e500: Extend address/size of / to 64bitAlexander Graf1-10/+18
We want to be able to support >= 4GB of RAM. To do so, we need to be able to tell the guest OS how much RAM it has. However, that information today is capped to 32bit. So let's extend the offset and size fields to 64bit, so we can fit in big addresses and even one day - if we wish to do so - map devices above 32bit. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: e500: Define addresses as always 64bitAlexander Graf1-17/+17
Every time we use an address constant, it needs to potentially fit into a 64bit physical address space. So let's define things accordingly. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: e500: Use new SOC dt formatAlexander Graf1-5/+4
Due to popular demand, let's clean up the soc node a bit and use more recent dt notions. Requested-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: e500: Use new MPIC dt formatAlexander Graf1-15/+18
Due to popular demand, we're updating the way we generate the MPIC node and interrupt lines based on what the current state of art is. Requested-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24Revert "dt: temporarily disable subtree creation failure check"Alexander Graf1-2/+0
This reverts commit "dt: temporarily disable subtree creation failure check" which was meant as a temporary solution to keep external and dynamic device tree construction intact. Now that we switched to fully dynamic dt construction, it's no longer necessary. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: e500: enable manual loading of dtb blobAlexander Graf1-4/+22
We want to be able to override the automatically created device tree by using the -dtb option. Implement this for the mpc8544ds machine. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: e500: dt: use target_phys_addr_t for ramsizeAlexander Graf1-1/+1
We're passing the ram size as uint32_t, capping it to 32 bits atm. Change to target_phys_addr_t (uint64_t) to make sure we have all the bits. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: e500: dt: use 64bit cell helperAlexander Graf1-3/+3
We have a nice 64bit helper to ease the device tree generation and make the code more readable when creating 64bit 2-cell parameters. Use it when generating the device tree. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24dt: Add -machine dumpdtb option to dump the current dtbAlexander Graf2-0/+22
Now that we are dynamically creating the dtb, it's really useful to be able to dump the created blob for debugging. This patch implements a -machine dumpdtb=<file> option for e500 that dumps the dtb exactly in the form the guest would get it to disk. It can then be analyzed by dtc to get information about the guest configuration. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: e500: dt: start with empty device treeAlexander Graf4-22/+1
Now that all of the device tree bits are generated during runtime, we can get rid of the device tree blob and instead start from scratch with an empty device tree. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: e500: dt: create pci node dynamicallyAlexander Graf3-46/+50
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: e500: dt: create global-utils node dynamicallyAlexander Graf2-6/+9
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: e500: dt: create mpic node dynamicallyAlexander Graf1-0/+16
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: e500: dt: create serial nodes dynamicallyAlexander Graf2-26/+35
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: e500: dt: create /soc8544 node dynamicallyAlexander Graf2-9/+17
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: e500: dt: create /chosen node dynamicallyAlexander Graf1-0/+1
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: e500: dt: create / node dynamicallyAlexander Graf3-5/+8
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: e500: dt: create /hypervisor node dynamicallyAlexander Graf3-3/+1
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: e500: dt: create /cpus node dynamicallyAlexander Graf3-5/+5
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: e500: dt: create memory node dynamicallyAlexander Graf3-9/+4
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24PPC: e500: require libfdtAlexander Graf2-6/+1
Now that we're moving all of the device tree generation from an external pre-execution generated blob to runtime generation using libfdt, we absolutely must have libfdt around. This requirement was there before already, as the only way to not require libfdt with e500 was to not use -kernel, which was the only way to boot the mpc8544ds machine. This patch only manifests said requirement in the build system. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24dt: add helper for 64bit cell addsAlexander Graf2-0/+9
Some times in the device tree, we find an array of 2 u32 cells that really are a single u64 value. This patch adds a helper to make the creation of these easy. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@petalogix.com>
2012-06-24dt: add helper for phandle allocationAlexander Graf2-0/+8
Phandle references work by having 2 pieces: - a "phandle" 1-cell property in the device tree node - a reference to the same value in a property we want to point to the other node To generate the 1-cell property, we need an allocation mechanism that gives us a unique number space. This patch adds an allocator for these properties. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24dt: add helper for empty dt creationAlexander Graf2-0/+38
We want to get rid of the concept of loading an external device tree and instead generate our own. However, to do this we need to also create a device tree template programatically. This patch adds a helper to create an empty device tree in memory. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@petalogix.com>
2012-06-24dt: add helper for phandle enumerationAlexander Graf2-1/+16
This patch adds a helper to search for a node's phandle by its path. This is especially useful when the phandle is part of an array, not just a single cell in which case qemu_devtree_setprop_phandle would be the easy choice. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@petalogix.com>
2012-06-24dt: temporarily disable subtree creation failure checkAlexander Graf1-0/+2
Usually we want to know when creating a subtree fails. However, while introducing this patch set we have to modify the device tree and some times have the code to create a subtree in both the binary tree and the dynamically created tree. So ignore failures about this for now and enable them once we got rid of the binary device tree. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24dt: add helper for phandle referencesAlexander Graf2-0/+11
Phandles are the fancy device tree name for "pointer to another node". To create a phandle property, we most likely want to reference to the node we're pointing to by its path. So create a helper that allows us to do so. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@petalogix.com>
2012-06-24dt: add helpers for multi-cell addsAlexander Graf1-0/+12
We have device tree helpers that allow us to create single cell (u32) wide properties. However, when creating properties that contain an array of cells, we need to jump through hoops, manually passing in an array with converted endianness. To ease the pain of this, create a generic macro helper that allows us to pass the cells as arguments. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@petalogix.com>
2012-06-24dt: allow add_subnode to create root subnodesAlexander Graf1-1/+6
Our subnode creation helper can't handle creation of root subnodes, like "/memory". Fix this by allowing the parent node to be an empty string, indicating the root node. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@petalogix.com>
2012-06-24raw-posix: Fix build without is_allocated supportKevin Wolf1-1/+8
Move the declaration of s into the #ifdef sections that actually make use of it. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24spapr: Add "memop" hypercallBenjamin Herrenschmidt4-1/+151
This adds a qemu-specific hypervisor call to the pseries machine which allows to do what amounts to memmove, memcpy and xor over regions of physical memory such as the framebuffer. This is the simplest way to get usable framebuffer speed from SLOF since the framebuffer isn't mapped in the VRMA and so would otherwise require an hcall per 8 bytes access. The performance is still not great but usable, and can be improved with a more complex implementation of the hcall itself if needed. This also adds some documentation for the qemu-specific hypercalls that we add to PAPR along with a new qemu,hypertas-functions property that mirrors ibm,hypertas-functions and provides some discoverability for the new calls. Note: I chose note to advertise H_RTAS to the guest via that mechanism. This is done on purpose, the guest uses the normal RTAS interfaces provided by qemu (including SLOF) which internally calls H_RTAS. We might in the future implement part (or even all) of RTAS inside the guest like IBM's firmware does and replace H_RTAS with some finer grained set of private hypercalls. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-06-24spapr_vscsi: Error handling fixesBenjamin Herrenschmidt1-1/+3
We were incorrectly g_free'ing an object that isn't allocated in one error path and failed to release it completely in another This fixes qemu crashes with some cases of IO errors. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Alexander Graf <agraf@suse.de>
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