summaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2018-03-02xlnx-zynqmp: Connect the RTC deviceAlistair Francis2-0/+16
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-02xlnx-zynqmp-rtc: Add basic time supportAlistair Francis3-0/+63
Allow the guest to determine the time set from the QEMU command line. This includes adding a trace event to debug the new time. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-02xlnx-zynqmp-rtc: Initial commitAlistair Francis3-0/+299
Initial commit of the ZynqMP RTC device. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell22-15/+1246
virtio,vhost,pci,pc: features, fixes and cleanups - documentation updates - vhost fixes - new crypto vhost device Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Thu 01 Mar 2018 16:27:25 GMT # gpg: using RSA key 281F0DB8D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: cryptodev-vhost-user: set the key length cryptodev-vhost-user: add crypto session handler cryptodev: add vhost support cryptodev: add vhost-user as a new cryptodev backend docs/vmcoreinfo: detail unsupported host format behaviour vhost: fix incorrect check in vhost_verify_ring_mappings vhost: avoid to start/stop virtqueue which is not ready vhost: fix memslot limit check docs: pcie: Spell out machine type needs for PCIe features docs: document virtio-balloon stats intel-iommu: Accept 64-bit writes to FEADDR virtio-pci: trivial fixes in error message vhost-user: fix memory leak Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20180301-v2' into ↵Peter Maydell40-606/+1222
staging - add query-cpus-fast and deprecate query-cpus, while adding s390 cpu information - remove s390x memory hotplug implementation, which is not useable in this form - add boot menu support in the s390-ccw bios - expose s390x guest crash information - fixes and cleaups # gpg: Signature made Thu 01 Mar 2018 12:54:47 GMT # gpg: using RSA key DECF6B93C6F02FAF # gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" # gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" # gpg: aka "Cornelia Huck <cohuck@kernel.org>" # gpg: aka "Cornelia Huck <cohuck@redhat.com>" # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck/tags/s390x-20180301-v2: (27 commits) s390x/tcg: fix loading 31bit PSWs with the highest bit set s390x: remove s390_get_memslot_count s390x/sclp: remove memory hotplug support s390x/cpumodel: document S390FeatDef.bit not applicable hmp: change hmp_info_cpus to use query-cpus-fast qemu-doc: deprecate query-cpus qmp: add architecture specific cpu data for query-cpus-fast qmp: add query-cpus-fast qmp: expose s390-specific CPU info s390x/tcg: add various alignment checks s390x/tcg: fix disabling/enabling DAT s390/stattrib: Make SaveVMHandlers data static s390x/cpu: expose the guest crash information pc-bios/s390: Rebuild the s390x firmware images with the boot menu changes s390-ccw: interactive boot menu for scsi s390-ccw: use zipl values when no boot menu options are present s390-ccw: set cp_receive mask only when needed and consume pending service irqs s390-ccw: read user input for boot index via the SCLP console s390-ccw: print zipl boot menu s390-ccw: read stage2 boot loader data to find menu ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01cryptodev-vhost-user: set the key lengthGonglei2-0/+7
Signed-off-by: Gonglei <arei.gonglei@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2018-03-01cryptodev-vhost-user: add crypto session handlerGonglei4-11/+175
Introduce two vhost-user meassges: VHOST_USER_CREATE_CRYPTO_SESSION and VHOST_USER_CLOSE_CRYPTO_SESSION. At this point, the QEMU side support crypto operation in cryptodev host-user backend. Signed-off-by: Gonglei <arei.gonglei@huawei.com> Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com> Signed-off-by: Jay Zhou <jianjay.zhou@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2018-03-01cryptodev: add vhost supportGonglei7-0/+398
Impliment the vhost-crypto's funtions, such as startup, stop and notification etc. Introduce an enum QCryptoCryptoDevBackendOptionsType in order to identify the cryptodev vhost backend is vhost-user or vhost-kernel-module (If exist). At this point, the cryptdoev-vhost-user works. Signed-off-by: Gonglei <arei.gonglei@huawei.com> Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com> Signed-off-by: Jay Zhou <jianjay.zhou@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2018-03-01cryptodev: add vhost-user as a new cryptodev backendGonglei7-0/+622
Usage: -chardev socket,id=charcrypto0,path=/path/to/your/socket -object cryptodev-vhost-user,id=cryptodev0,chardev=charcrypto0 -device virtio-crypto-pci,id=crypto0,cryptodev=cryptodev0 Signed-off-by: Gonglei <arei.gonglei@huawei.com> Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com> Signed-off-by: Jay Zhou <jianjay.zhou@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2018-03-01docs/vmcoreinfo: detail unsupported host format behaviourMarc-André Lureau1-0/+4
Suggested-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2018-03-01vhost: fix incorrect check in vhost_verify_ring_mappingsJia He1-2/+2
In commit 0ca1fd2d6878 ("vhost: Simplify ring verification checks"), it checks the virtqueue desc mapping for 3 times. Fixed: commit 0ca1fd2d6878 ("vhost: Simplify ring verification checks") Signed-off-by: Jia He <jia.he@hxt-semitech.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2018-03-01vhost: avoid to start/stop virtqueue which is not readyJia He1-1/+17
In our Armv8a server, we try to configure the vhost scsi but fail to boot up the guest (-machine virt-2.10). The guest's boot failure is very early, even earlier than grub. There are 3 virtqueues (ctrl, event and cmd) for virtio scsi device, but ovmf and seabios will only set the physical address for the 3rd one (cmd). Then in vhost_virtqueue_start(), virtio_queue_get_desc_addr will be 0 for ctrl and event vq when qemu negotiates with ovmf. So vhost_memory_map fails with ENOMEM. This patch just fixs it by early quitting the virtqueue start/stop when virtio_queue_get_desc_addr is 0. Btw, after guest kernel starts, all the 3 queues will be initialized and set address correctly. Already tested on Arm64 and X86_64 qemu. Signed-off-by: Jia He <jia.he@hxt-semitech.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2018-03-01Merge remote-tracking branch ↵Peter Maydell23-466/+1976
'remotes/pmaydell/tags/pull-target-arm-20180301' into staging target-arm queue: * update MAINTAINERS for Alistair's new email address * add Arm v8.2 FP16 arithmetic extension for linux-user * implement display connector emulation for vexpress board * xilinx_spips: Enable only two slaves when reading/writing with stripe * xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands * hw: register: Run post_write hook on reset # gpg: Signature made Thu 01 Mar 2018 11:22:46 GMT # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180301: (42 commits) MAINTAINERS: Update my email address linux-user: Report AArch64 FP16 support via hwcap bits target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU arm/translate-a64: add all single op FP16 to handle_fp_1src_half arm/translate-a64: implement simd_scalar_three_reg_same_fp16 arm/translate-a64: add all FP16 ops in simd_scalar_pairwise arm/translate-a64: add FP16 FMOV to simd_mod_imm arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16 arm/helper.c: re-factor rsqrte and add rsqrte_f16 arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16 arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16 arm/translate-a64: add FP16 FRECPE arm/helper.c: re-factor recpe and add recepe_f16 arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16 arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16 arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16 arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16 arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16 arm/translate-a64: initial decode for simd_two_reg_misc_fp16 arm/translate-a64: add FP16 x2 ops for simd_indexed ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01vhost: fix memslot limit checkJay Zhou1-7/+12
Since used_memslots will be updated to the actual value after registering memory listener for the first time, move the memslots limit checking to the right place. Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Jay Zhou <jianjay.zhou@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2018-03-01docs: pcie: Spell out machine type needs for PCIe featuresKashyap Chamarthy1-2/+7
PCIe features are available only via the 'q35' machine type for x86 and the 'virt' machine type for AArch64 architecture. Mention that explicitly. Thanks: Daniel Berrangé Signed-off-by: Kashyap Chamarthy <kchamart@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2018-03-01docs: document virtio-balloon statsTomáš Golembiovský1-0/+2
Document statistics added in commits commit a0d06486b445985b8d128df172daefbae205bffd Author: Denis V. Lunev <den@openvz.org> Date: Wed Feb 24 10:50:48 2016 +0300 virtio-balloon: add 'available' counter and commit bf1e7140ef0b3a149860ab9f05b36665133238f6 Author: Tomáš Golembiovský <tgolembi@redhat.com> Date: Tue Dec 5 13:14:46 2017 +0100 virtio-balloon: include statistics of disk/file caches Signed-off-by: Tomáš Golembiovský <tgolembi@redhat.com> Reviewed-by: Jonathan Helman <jonathan.helman@oracle.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2018-03-01intel-iommu: Accept 64-bit writes to FEADDRJan Kiszka1-2/+9
Xen is doing this [1] and currently triggers an abort. [1] http://xenbits.xenproject.org/gitweb/?p=xen.git;a=blob;f=xen/drivers/passthrough/vtd/iommu.c;h=daaed0abbdd06b6ba3d948ea103aadf02651e83c;hb=refs/heads/master#l1108 Reported-by: Luis Lloret <luis_lloret@mentor.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2018-03-01virtio-pci: trivial fixes in error messageGreg Kurz1-1/+1
Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2018-03-01vhost-user: fix memory leaklinzhecheng1-0/+1
g_free() was moved from vhost_net_cleanup in commit e6bcb1b, so we should free net after vhost_net_cleanup Signed-off-by: linzhecheng <linzhecheng@huawei.com> Reviewed-by: Marc-André Lureau < marcandre.lureau@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-03-01Merge remote-tracking branch 'remotes/famz/tags/staging-pull-request' into ↵Peter Maydell2-4/+8
staging Block patches 2018-03-01 Coverity fixes for nvme:// # gpg: Signature made Thu 01 Mar 2018 07:24:24 GMT # gpg: using RSA key CA35624C6A9171C6 # gpg: Good signature from "Fam Zheng <famz@redhat.com>" # Primary key fingerprint: 5003 7CB7 9706 0F76 F021 AD56 CA35 624C 6A91 71C6 * remotes/famz/tags/staging-pull-request: block/nvme: fix Coverity reports Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01s390x/tcg: fix loading 31bit PSWs with the highest bit setDavid Hildenbrand1-0/+4
Let's also put the 31-bit hack in front of the REAL MMU, otherwise right now we get errors when loading a PSW where the highest bit is set (e.g. via s390-netboot.img). The highest bit is not masked away, therefore we inject addressing exceptions into the guest. The proper fix will later be to do all address wrapping before accessing the MMU - so we won't get any "wrong" entries in there (which makes flushing also easier). But that will require more work (wrapping in load_psw, wrapping when incrementing the PC, wrapping every memory access). This fixes the tests/pxe-test test. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180301120826.6847-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-03-01Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-signed' into ↵Peter Maydell1-9/+11
staging qemu-sparc update # gpg: Signature made Tue 27 Feb 2018 19:03:28 GMT # gpg: using RSA key 5BC2C56FAE0F321F # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" # Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F * remotes/mcayland/tags/qemu-sparc-signed: loader: don't perform overlapping address check for memory region ROM images Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01MAINTAINERS: Update my email addressAlistair Francis1-6/+6
I am leaving Xilinx, so to avoid having an email address that bounces update my maintainer address to point to my personal email address. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Alistair Francis <alistair@alistair23.me> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 7bb690382e3370aa1c1e047a84e36603c787ec0e.1519749987.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01linux-user: Report AArch64 FP16 support via hwcap bitsPeter Maydell1-0/+2
Set the appropriate Linux hwcap bits to tell the guest binary if we have implemented half-precision floating point support. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-03-01target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPUPeter Maydell1-0/+1
Now we have implemented FP16 we can enable it for the "any" CPU. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [PMM: split out from an earlier patch in the series] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01arm/translate-a64: add all single op FP16 to handle_fp_1src_halfAlex Bennée1-0/+71
This includes FMOV, FABS, FNEG, FSQRT and FRINT[NPMZAXI]. We re-use existing helpers to achieve this. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227143852.11175-32-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01arm/translate-a64: implement simd_scalar_three_reg_same_fp16Alex Bennée1-0/+99
This covers the encoding group: Advanced SIMD scalar three same FP16 As all the helpers are already there it is simply a case of calling the existing helpers in the scalar context. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227143852.11175-31-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01arm/translate-a64: add all FP16 ops in simd_scalar_pairwiseAlex Bennée1-26/+54
I only needed to do a little light re-factoring to support the half-precision helpers. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227143852.11175-30-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01arm/translate-a64: add FP16 FMOV to simd_mod_immAlex Bennée1-10/+25
Only one half-precision instruction has been added to this group. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227143852.11175-29-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16Alex Bennée1-0/+7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227143852.11175-28-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01arm/helper.c: re-factor rsqrte and add rsqrte_f16Alex Bennée2-118/+104
Much like recpe the ARM ARM has simplified the pseudo code for the calculation which is done on a fixed point 9 bit integer maths. So while adding f16 we can also clean this up to be a little less heavy on the floating point and just return the fractional part and leave the calle's to do the final packing of the result. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227143852.11175-27-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16Alex Bennée3-0/+19
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227143852.11175-26-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16Alex Bennée3-0/+34
We go with the localised helper. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227143852.11175-25-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01arm/translate-a64: add FP16 FRECPEAlex Bennée1-0/+8
Now we have added f16 during the re-factoring we can simply call the helper. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227143852.11175-24-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01arm/helper.c: re-factor recpe and add recepe_f16Alex Bennée2-97/+128
It looks like the ARM ARM has simplified the pseudo code for the calculation which is done on a fixed point 9 bit integer maths. So while adding f16 we can also clean this up to be a little less heavy on the floating point and just return the fractional part and leave the calle's to do the final packing of the result. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227143852.11175-23-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16Alex Bennée1-1/+15
Neither of these operations alter the floating point status registers so we can do a pure bitwise operation, either squashing any sign bit (ABS) or inverting it (NEG). Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227143852.11175-22-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16Alex Bennée3-24/+104
I've re-factored the handle_simd_intfp_conv helper to properly handle half-precision as well as call plain conversion helpers when we are not doing fixed point conversion. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227143852.11175-21-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16Alex Bennée1-23/+57
I re-use the existing handle_2misc_fcmp_zero handler and tweak it slightly to deal with the half-precision case. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227143852.11175-20-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16Alex Bennée3-1/+118
This covers all the floating point convert operations. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227143852.11175-19-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16Alex Bennée3-5/+142
This adds the full range of half-precision floating point to integral instructions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227143852.11175-18-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01arm/translate-a64: initial decode for simd_two_reg_misc_fp16Alex Bennée1-0/+40
This actually covers two different sections of the encoding table: Advanced SIMD scalar two-register miscellaneous FP16 Advanced SIMD two-register miscellaneous (FP16) The difference between the two is covered by a combination of Q (bit 30) and S (bit 28). Notably the FRINTx instructions are only available in the vector form. This is just the decode skeleton which will be filled out by later patches. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227143852.11175-17-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01arm/translate-a64: add FP16 x2 ops for simd_indexedAlex Bennée3-6/+76
A bunch of the vectorised bitwise operations just operate on larger chunks at a time. We can do the same for the new half-precision operations by introducing some TWOHALFOP helpers which work on each half of a pair of half-precision operations at once. Hopefully all this hoop jumping will get simpler once we have generically vectorised helpers here. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227143852.11175-16-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexedAlex Bennée1-16/+66
The helpers use the new re-factored muladd support in SoftFloat for the float16 work. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180227143852.11175-15-alex.bennee@linaro.org Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16Alex Bennée1-75/+133
This includes FMAXNMP, FADDP, FMAXP, FMINNMP, FMINP. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227143852.11175-14-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16Alex Bennée4-4/+54
As some of the constants here will also be needed elsewhere (specifically for the upcoming SVE support) we move them out to softfloat.h. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227143852.11175-13-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16Alex Bennée3-0/+41
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227143852.11175-12-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16Alex Bennée3-0/+69
These use the generic float16_compare functionality which in turn uses the common float_compare code from the softfloat re-factor. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227143852.11175-11-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16Alex Bennée3-0/+36
The fprintf is only there for debugging as the skeleton is added to, it will be removed once the skeleton is complete. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227143852.11175-10-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01arm/translate-a64: initial decode for simd_three_reg_same_fp16Alex Bennée1-0/+73
This is the initial decode skeleton for the Advanced SIMD three same instruction group. The fprintf is purely to aid debugging as the additional instructions are added. It will be removed once the group is complete. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227143852.11175-9-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-01arm/translate-a64: handle_3same_64 comment fixAlex Bennée1-2/+1
We do implement all the opcodes. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227143852.11175-8-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.2.1 (git 2.18.0) at 2024-07-13 03:22:17 +0000