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2012-12-14PPC: E500: Move PCI slot information into paramsAlexander Graf4-1/+9
We have a params struct that allows us to expose differences between e500 machine models. Include PCI slot information there, so we can have different machines with different PCI slot topology. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14PPC: E500: Generate dt pci irq map dynamicallyAlexander Graf1-20/+31
Today we're hardcoding the PCI interrupt map in the e500 machine file. Instead, let's write it dynamically so that different machine types can have different slot properties. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14PPC: E500: PCI: Make IRQ calculation more genericAlexander Graf1-10/+3
The IRQ line calculation is more or less hardcoded today. Instead, let's write it as an algorithmic function that theoretically allows an arbitrary number of PCI slots. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14PPC: E500: PCI: Make first slot qdev settableAlexander Graf1-1/+8
Today the first slot id in our e500 pci implementation is hardcoded to 0x11. Keep it there as default, but allow users to change the default to a different id. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14openpic: Accelerate pending irq searchAlexander Graf1-0/+11
When we're done with one interrupt, we need to search for the next pending interrupt in the queue. This search has grown quite big now that we have more than 256 possible irq lines. So let's memorize how many interrupts we have pending in our bitmaps, so that we can always bail out in the usual case - the one where we're all done. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14openpic: fix minor coding style issuesAlexander Graf1-6/+6
This patch removes all remaining occurences of spaces before function parameter indicating parenthesis. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14MSI-X: Fix endiannessAlexander Graf1-4/+2
The MSI-X vector tables are usually stored in little endian in memory, so let's mark the accessors as such. This fixes MSI-X on e500 for me. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Michael S. Tsirkin <mst@redhat.com>
2012-12-14PPC: e500: Declare pci bridge as bridgeAlexander Graf1-0/+6
The new PCI host bridge device needs to identify itself as PCI host bridge. Declare it as such. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14PPC: e500: Add MSI supportAlexander Graf1-0/+23
Now that our interrupt controller supports MSIs, let's expose that feature to the guest through the device tree! Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14openpic: add Shared MSI supportAlexander Graf1-20/+130
The OpenPIC allows MSI access through shared MSI registers. Implement them for the MPC8544 MPIC, so we can support MSIs. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14openpic: make brr1 model specificAlexander Graf1-1/+4
Now that we can properly distinguish between openpic model differences, let's move brr1 out of the raven code path. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14openpic: convert to qdevAlexander Graf4-155/+180
This patch converts the OpenPIC device to qdev. Along the way it renames the "openpic" target to "raven" and the "mpic" target to "fsl_mpic_20", to better reflect the actual models they implement. This way we have a generic OpenPIC device now that can handle different flavors of the OpenPIC specification. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14openpic: remove irq_outAlexander Graf4-10/+6
The current openpic emulation contains half-ready code for bypass mode. Remove it, so that when someone wants to finish it they can start from a clean state. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14openpic: rename openpic_t to OpenPICStateAlexander Graf1-34/+34
Rename the openpic_t struct to OpenPICState, so it adheres better to the current coding style rules. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14openpic: convert simple reg operations to builtin bitopsAlexander Graf1-31/+36
The openpic code has its own bitmap code to access bits inside of a bitmap. However, that is overkill when we simply want to check for a bit inside of a uint32_t. So instead, let's use normal bit masks and C builtin shifts and ands. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14openpic: remove unused type variableAlexander Graf1-25/+2
The openpic source irqs are carrying around a type indicator that is never accessed by anything. Remove it. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14openpic: unify memory api subregionsAlexander Graf1-52/+56
The only difference between the "openpic" and "mpic" memory api subregion descriptors is the endianness. Unify them as openpic accessors with explicit endianness markers in their names. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14openpic: combine openpic and mpic reset functionsAlexander Graf1-61/+42
The openpic and mpic reset handlers are almost identical. Combine them and extract the differences into state variables. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14openpic: merge mpic and openpic timer handlingAlexander Graf1-100/+31
The openpic and mpic timer handling code is basically the same. Merge them. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14openpic: combine mpic and openpic irq raise functionsAlexander Graf2-18/+19
The IRQ raise mechanisms of the OpenPIC and MPIC controllers is identical, just that the MPIC one can also raise critical interrupts. Combine those two and check for critical raise capability during runtime. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14openpic: Convert subregions to memory apiAlexander Graf1-45/+61
The "openpic" controller is currently using one big region and does subregion dispatching manually. Move this to the memory api. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14openpic: combine mpic and openpic src handlersAlexander Graf1-47/+5
The MPIC source irq handler suddenly became identical to the standard OpenPIC source irq handler. Combine them into the same function. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14openpic: update to proper memory apiAlexander Graf1-90/+48
The openpic code was still using the old mmio memory api. Convert it to be a generic memory api user and clean up some code that becomes redundant that way. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14mpic: Unify numbering schemeAlexander Graf2-249/+45
MPIC interrupt numbers in Linux (device tree) and in QEMU are different, because QEMU takes the sparseness of the IRQ number space into account. Remove that cleverness and instead assume a flat number space. This makes the code easier to understand, because we are actually aligned with Linux on the view of our worlds. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14openpic: Remove unused codeAlexander Graf1-163/+0
The openpic code had a few WIP bits left that nobody reanimated within the last few years. Remove that code. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Hervé Poussineau <hpoussin@reactos.org>
2012-12-14pseries: Don't allow TCE (iommu) tables to be registered with duplicate LIOBNsDavid Gibson1-0/+6
The PAPR specification requires that every bus or device mediated by the IOMMU have a unique Logical IO Bus Number (LIOBN). This patch adds a check to enforce this, which will help catch errors in configuration earlier. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14Adding BAR0 for e500 PCI controllerBharat Bhushan3-10/+91
PCI Root complex have TYPE-1 configuration header while PCI endpoint have type-0 configuration header. The type-1 configuration header have a BAR (BAR0). In Freescale PCI controller BAR0 is used for mapping pci address space to CCSR address space. This can used for 2 purposes: 1) for MSI interrupt generation 2) Allow CCSR registers access when configured as PCI endpoint, which I am not sure is a use case with QEMU-KVM guest. What I observed is that when guest read the size of BAR0 of host controller configuration header (TYPE1 header) then it always reads it as 0. When looking into the QEMU hw/ppce500_pci.c, I do not find the PCI controller device registering BAR0. I do not find any other controller also doing so may they do not use BAR0. There are two issues when BAR0 is not there (which I can think of): 1) There should be BAR0 emulated for PCI Root complex (TYPE1 header) and when reading the size of BAR0, it should give size as per real h/w. 2) Do we need this BAR0 inbound address translation? When BAR0 is of non-zero size then it will be configured for PCI address space to local address(CCSR) space translation on inbound access. The primary use case is for MSI interrupt generation. The device is configured with an address offsets in PCI address space, which will be translated to MSI interrupt generation MPIC registers. Currently I do not understand the MSI interrupt generation mechanism in QEMU and also IIRC we do not use QEMU MSI interrupt mechanism on e500 guest machines. But this BAR0 will be used when using MSI on e500. I can see one more issue, There are ATMUs emulated in hw/ppce500_pci.c, but i do not see these being used for address translation. So far that works because pci address space and local address space are 1:1 mapped. BAR0 inbound translation + ATMU translation will complete the address translation of inbound traffic. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> [agraf: fix double variable assignment w/o read] Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14e500: Adding CCSR memory regionBharat Bhushan1-23/+40
All devices are also placed under CCSR memory region. The CCSR memory region is exported to pci device. The MSI interrupt generation is the main reason to export the CCSR region to PCI device. This put the requirement to move mpic under CCSR region, but logically all devices should be under CCSR. So this patch places all emulated devices under ccsr region. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14pseries: Update SLOF for NVRAM supportDavid Gibson3-1/+1
Now that we have implemented PAPR compatible NVRAM interfaces in qemu, this updates the SLOF firmware to actually initialize and use the NVRAM as a PAPR guest firmware is expected to do. This SLOF update also includes an ugly but useful workaround for a bug in the SLES11 installer which caused it to fail under KVM. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14pseries: Implement PAPR NVRAMDavid Gibson5-1/+236
The PAPR specification requires a certain amount of NVRAM, accessed via RTAS, which we don't currently implement in qemu. This patch addresses this deficiency, implementing the NVRAM as a VIO device, with some glue to instantiate it automatically based on a machine option. The machine option specifies a drive id, which is used to back the NVRAM, making it persistent. If nothing is specified, the driver instead simply allocates space for the NVRAM, which will not be persistent Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14pseries: Split xics irq configuration from state informationDavid Gibson1-12/+8
Currently the XICS irq controller code has a per-irq state structure which amongst other things includes whether the interrupt is level or message triggered - this is configured by the platform code, and is not directly visible to the guest. This leads to a slightly awkward construct at reset time where we need to reset everything in the state structure _except_ the lsi/msi flag, which needs to retain the information given at platform init time. More importantly this flag will make matching the qemu state to the KVM state for the upcoming in-kernel XICS implementation more awkward. This patch, therefore, removes this flag from the per-irq state structure, instead adding a parallel array giving the lsi/msi configuration per irq. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14pseries: Add tracepoints to the XICS interrupt controllerDavid Gibson2-3/+33
This patch adds tracing / debugging calls to the XICS interrupt controller implementation used on the pseries machine. Signed-off-by: Ben Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14pseries: Allow RTAS tokens without a qemu handlerBen Herrenschmidt1-1/+1
Kernel-based RTAS calls will not have a qemu handler, but will still be registered in qemu in order to be assigned a token number and appear in the device-tree. Let's test for the name being NULL rather than the handler when deciding to skip an entry while building the device-tree Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14pseries: Return the token when we register an RTAS callMichael Ellerman2-3/+3
The kernel will soon be able to service some RTAS calls. However the choice of tokens will still be up to userspace. To support this have spapr_rtas_register() return the token that is allocated for an RTAS call, that allows the calling code to tell the kernel what the token value is. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14pseries: Use #define for XICS base irq numberBen Herrenschmidt3-2/+3
Currently the lowest "real" irq number for the XICS irq controller (as opposed to numbers reserved for IPIs and other special purposes) is hard coded as 16 in two places - in xics_system_init() and in spapr.c. As well as being generally bad practice, we're going to need to change this number soon to fit in with the in-kernel XICS implementation. This patch adds a #define for this number to avoid future breakage. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Ben Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14pseries: Fix incorrect initialization of interrupt controllerDavid Gibson1-1/+1
Currently in the reset code for the XICS interrupt controller, we initialize the pending_priority field to 0 (most favored, by XICS convention). This is incorrect, since there is no pending interrupt, it should be set to least favored - 0xff. At the moment our XICS implementation doesn't get hurt by this edge case, but it does confuse the upcoming kernel XICS implementation. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-13Merge remote-tracking branch 'kwolf/for-anthony' into stagingAnthony Liguori52-443/+1343
* kwolf/for-anthony: (43 commits) qcow2: Factor out handle_dependencies() qcow2: Execute run_dependent_requests() without lock qcow2: Enable dirty flag in qcow2_alloc_cluster_link_l2 qcow2: Allocate l2meta only for cluster allocations qcow2: Drop l2meta.cluster_offset qcow2: Allocate l2meta dynamically qcow2: Introduce Qcow2COWRegion qcow2: Round QCowL2Meta.offset down to cluster boundary atapi: reset cdrom tray statuses on ide_reset qemu-iotests: Test concurrent cluster allocations qcow2: Move BLKDBG_EVENT out of the lock qemu-io: Add AIO debugging commands blkdebug: Implement suspend/resume of AIO requests blkdebug: Factor out remove_rule() blkdebug: Allow usage without config file create new function: qemu_opt_set_number use qemu_opts_create_nofail introduce qemu_opts_create_nofail function qemu-option: qemu_opt_set_bool(): fix code duplication qemu-option: qemu_opts_validate(): fix duplicated code ... Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-12-13Merge remote-tracking branch 'pmaydell/arm-devs.next' into stagingAnthony Liguori9-37/+106
* pmaydell/arm-devs.next: hw/ds1338.c: Fix handling of DAY (wday) register. hw/ds1338.c: Implement support for the control register. hw/ds1338.c: Ensure state is properly initialized. hw/ds1338.c: Fix handling of HOURS register. hw/ds1338.c: Add definitions for various flags in the RTC registers. hw/ds1338.c: Correct bug in conversion to BCD. exynos4210/mct: Avoid infinite loop on non incremental timers hw/arm_gic: fix target CPUs affected by set enable/pending ops xilinx_zynq: Add one variable to avoid overwriting QSPI bus hw/arm_gic_common: Correct GICC_PMR reset value for newer GICs hw/arm_gic: Fix comparison with priority mask register hw/arm_boot, exynos4210, highbank: Fix secondary boot GIC init Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-12-13Merge remote-tracking branch 'kraxel/seabios-e8a76b0' into stagingAnthony Liguori4-0/+0
* kraxel/seabios-e8a76b0: seabios: update to e8a76b0f225bba5ba9d63ab227e0a37b3beb1059 Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-12-13qMerge remote-tracking branch 'awilliam/tags/vfio-pci-for-qemu-20121210.0' ↵Anthony Liguori1-2/+3
into staging vfio-pci: fix kvm disabled path * awilliam/tags/vfio-pci-for-qemu-20121210.0: vfio-pci: Don't use kvm_irqchip_in_kernel Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-12-13qcow2: Factor out handle_dependencies()Kevin Wolf1-28/+42
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2012-12-13qcow2: Execute run_dependent_requests() without lockKevin Wolf1-20/+16
There's no reason for run_dependent_requests() to hold s->lock, and a later patch will require that in fact the lock is not held. Also, before this patch, run_dependent_requests() not only does what its name suggests, but also removes the l2meta from the list of in-flight requests. When changing this, it becomes an one-liner, so just inline it completely. Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2012-12-13qcow2: Enable dirty flag in qcow2_alloc_cluster_link_l2Kevin Wolf3-7/+7
This is closer to where the dirty flag is really needed, and it avoids having checks for special cases related to cluster allocation directly in the writev loop. Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2012-12-13qcow2: Allocate l2meta only for cluster allocationsKevin Wolf3-31/+31
Even for writes to already allocated clusters, an l2meta is allocated, though it stays effectively unused. After this patch, only allocating requests still have one. Each l2meta now describes an in-flight request that writes to clusters that are not yet hooked up in the L2 table. Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2012-12-13qcow2: Drop l2meta.cluster_offsetKevin Wolf3-15/+14
There's no real reason to have an l2meta for normal requests that don't allocate anything. Before we can get rid of it, we must return the host cluster offset in a different way. Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2012-12-13qcow2: Allocate l2meta dynamicallyKevin Wolf1-11/+15
As soon as delayed COW is introduced, the l2meta struct is needed even after completion of the request, so it can't live on the stack. Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2012-12-13qcow2: Introduce Qcow2COWRegionKevin Wolf2-36/+76
This makes it easier to address the areas for which a COW must be performed. As a nice side effect, the COW code in qcow2_alloc_cluster_link_l2 becomes really trivial. Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2012-12-13qcow2: Round QCowL2Meta.offset down to cluster boundaryKevin Wolf2-2/+24
The offset within the cluster is already present as n_start and this is what the code uses. QCowL2Meta.offset is only needed at a cluster granularity. Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2012-12-13hw/ds1338.c: Fix handling of DAY (wday) register.Antoine Mathys1-3/+12
Per the datasheet, the DAY (wday) register is user defined. Implement this. Signed-off-by: Antoine Mathys <barsamin@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-12-13hw/ds1338.c: Implement support for the control register.Antoine Mathys1-4/+13
Signed-off-by: Antoine Mathys <barsamin@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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