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2016-10-07async: add aio_bh_schedule_oneshotPaolo Bonzini2-4/+29
qemu_bh_delete is already clearing bh->scheduled at the same time as it's setting bh->deleted. Since it's not using any memory barriers, there is no synchronization going on for bh->deleted, and this makes the bh->deleted checks superfluous in aio_compute_timeout, aio_bh_poll and aio_ctx_check. Just remove them, and put the (bh->scheduled && bh->deleted) combo to work in a new function aio_bh_schedule_oneshot. The new function removes the need to save the QEMUBH pointer between the creation and the execution of the bottom half. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2016-10-07block: use bdrv_add_before_write_notifierPaolo Bonzini1-2/+1
Register the notifier using the specific API for block devices. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2016-10-06Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.8-20161006' ↵Peter Maydell45-179/+930
into staging ppc patch queue 2016-10-06 Currently accumulated target-ppc and spapr machine related patches. - More POWER9 instruction implementations - Additional test case / enabling of test cases for Power - Assorted fixes # gpg: Signature made Thu 06 Oct 2016 07:05:07 BST # gpg: using RSA key 0x6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.8-20161006: (29 commits) hw/ppc/spapr: Use POWER8 by default for the pseries-2.8 machine tests/pxe: Use -nodefaults to speed up ppc64/ipv6 pxe test spapr: fix check of cpu alias name in spapr_get_cpu_core_type() tests: enable ohci/uhci/xhci tests on PPC64 libqos: use generic qtest_shutdown() libqos: add PCI management in qtest_vboot()/qtest_shutdown() libqos: add PPC64 PCI support target-ppc: fix vmx instruction type/type2 target-ppc/kvm: Enable transactional memory on POWER8 with KVM-HV, too target-ppc/kvm: Add a wrapper function to check for KVM-PR MAINTAINERS: Add two more ppc related files target-ppc: Implement mtvsrws instruction target-ppc: add vclzlsbb/vctzlsbb instructions target-ppc: add vector compare not equal instructions target-ppc: fix invalid mask - cmpl, bctar target-ppc: add stxvb16x instruction target-ppc: add lxvb16x instruction target-ppc: add stxvh8x instruction target-ppc: add lxvh8x instruction target-ppc: improve stxvw4x implementation ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-06rules.mak: quiet-command: Split command name and args to printPeter Maydell12-100/+106
The quiet-command make rule currently takes two arguments: the command and arguments to run, and a string to print if the V flag is not set (ie we are not being verbose). By convention, the string printed is of the form " NAME some args". Unfortunately to get nicely lined up output all the strings have to agree about what column the arguments should start in, which means that if we add a new quiet-command usage which wants a slightly longer CMD name then we either put up with misalignment or change every quiet-command string. Split the quiet-mode string into two, the "NAME" and the "same args" part, and use printf(1) to format the string automatically. This means we only need to change one place if we want to support a longer maximum name. In particular, we can now print 7-character names lined up properly (they are needed for the OSX "SETTOOL" invocation). Change all the uses of quiet-command to the new syntax. (Any which are missed or inadvertently reintroduced via later merges will result in slightly misformatted quiet output rather than disaster.) A few places in the pc-bios/ makefiles are updated to use "BUILD", "SIGN" and "STRIP" rather than "Building", "Signing" and "Stripping" for consistency and to keep them below 7 characters. Module .mo links now print "LD" rather than the nonstandard "LD -r". Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Blake <eblake@redhat.com> Message-id: 1475598441-27908-1-git-send-email-peter.maydell@linaro.org
2016-10-06hw/ppc/spapr: Use POWER8 by default for the pseries-2.8 machineThomas Huth2-1/+6
A couple of distributors are compiling their distributions with "-mcpu=power8" for ppc64le these days, so the user sooner or later runs into a crash there when not explicitely specifying the "-cpu POWER8" option to QEMU (which is currently using POWER7 for the "pseries" machine by default). Due to this reason, the linux-user target already switched to POWER8 a while ago (see commit de3f1b98410e0d5b406a0df3a48547b559d18602). Since the softmmu target of course has the same problem, we should switch there to POWER8 for the newer machine types, too. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-06tests/pxe: Use -nodefaults to speed up ppc64/ipv6 pxe testThomas Huth1-2/+2
SLOF is unfortunately quite slow when running with TCG, so the pxe test is also performing rather slow here. By using "-nodefaults" we can disable some devices (vscsi) that we are not interested in here, so that SLOF does not have to scan them during boot and thus starts up a little bit faster. The ppc64 pxe-test now only takes 27 seconds on my laptop instead of 33 seconds. The "-nodefaults" flag seems to work fine for the x86 tests, too, so it is added here unconditionally here (though there is no speed-up on x86 by using this flag). Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-06spapr: fix check of cpu alias name in spapr_get_cpu_core_type()Greg Kurz1-4/+4
If the user passes an alias name and a property to -cpu, QEMU fails to find the CPU definition and exits. $ qemu-system-ppc64 -cpu POWER8E,compat=power7 qemu-system-ppc64: Unable to find sPAPR CPU Core definition This happens because spapr_get_cpu_core_type() passes the full string from the command line (i.e. "POWER8E,compat=power7") to ppc_cpu_lookup_alias(), instead of the alias name piece only (i.e. "POWER8E"). The fix is to pass model_pieces[0] to ppc_cpu_lookup_alias(). Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-06tests: enable ohci/uhci/xhci tests on PPC64Laurent Vivier2-9/+23
Signed-off-by: Laurent Vivier <lvivier@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-06libqos: use generic qtest_shutdown()Laurent Vivier5-6/+21
Machine specific shutdown function can be registered by the machine specific qtest_XXX_boot() if needed. So we will not have to test twice the architecture (on boot and on shutdown) if the test can be run on several architectures. Signed-off-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-06libqos: add PCI management in qtest_vboot()/qtest_shutdown()Laurent Vivier21-25/+46
Signed-off-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-06libqos: add PPC64 PCI supportLaurent Vivier7-23/+376
Signed-off-by: Laurent Vivier <lvivier@redhat.com> [dwg: Fixed build problem on 32-bit hosts] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05target-ppc: fix vmx instruction type/type2Nikunj A Dadhania2-24/+24
A few of the new instructions added inadvertently changed the type of old instruction(PPC_ALTIVEC) to PPC2_ALTIVEC_207 in the dual form declaration. commit: b5d569a1 (target-ppc: add vector extract instructions) commit: e7b1e06f (target-ppc: add vector insert instructions) commit: 3aa56a19 (target-ppc: add vector compare not equal instructions) New ISA 3.0 instructions added: vextractub PPC_NONE PPC2_ISA300 vextractuh PPC_NONE PPC2_ISA300 vextractuw PPC_NONE PPC2_ISA300 vinsertb PPC_NONE PPC2_ISA300 vinserth PPC_NONE PPC2_ISA300 vinsertw PPC_NONE PPC2_ISA300 vcmpneb PPC_NONE PPC2_ISA300 vcmpneh PPC_NONE PPC2_ISA300 vcmpnew PPC_NONE PPC2_ISA300 Affected older instructions: vspltb PPC_ALTIVEC PPC_NONE vsplth PPC_ALTIVEC PPC_NONE vspltw PPC_ALTIVEC PPC_NONE vspltisb PPC_ALTIVEC PPC_NONE vspltish PPC_ALTIVEC PPC_NONE vspltisw PPC_ALTIVEC PPC_NONE vcmpequb PPC_ALTIVEC PPC_NONE vcmpequh PPC_ALTIVEC PPC_NONE vcmpequw PPC_ALTIVEC PPC_NONE Change the instruction type/type2 for the older instructions back to what it was(PPC_ALTIVEC). CC: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com> Reported-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05target-ppc/kvm: Enable transactional memory on POWER8 with KVM-HV, tooThomas Huth1-1/+8
Transactional memory is also supported on POWER8 KVM-HV if the KVM_CAP_PPC_HTM is not available in the kernel yet, so add a hack to allow TM here, too. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05target-ppc/kvm: Add a wrapper function to check for KVM-PRThomas Huth1-10/+16
It makes more sense if we have a proper function to check for KVM-PR than to check for the GET_PVINFO extension all over the place. Signed-off-by: Thomas Huth <thuth@redhat.com> [dwg: Expanded a comment to discourage overuse of this function] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05MAINTAINERS: Add two more ppc related filesThomas Huth1-0/+2
The file hw/intc/heathrow_pic.c belongs to the Old World Mac machine, and pc-bios/ppc_rom.bin belongs to the PReP machine. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05target-ppc: Implement mtvsrws instructionRavi Bangoria2-0/+20
mtvsrws: Move To VSR Word & Splat Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05target-ppc: add vclzlsbb/vctzlsbb instructionsRajalakshmi Srinivasaraghavan4-0/+48
The following vector instructions are added from ISA 3.0. vclzlsbb - Vector Count Leading Zero Least-Significant Bits Byte vctzlsbb - Vector Count Trailing Zero Least-Significant Bits Byte Signed-off-by: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05target-ppc: add vector compare not equal instructionsRajalakshmi Srinivasaraghavan4-16/+38
The following vector compare not equal instructions are added from ISA 3.0. vcmpneb - Vector Compare Not Equal Byte vcmpneh - Vector Compare Not Equal Halfword vcmpnew - Vector Compare Not Equal Word Signed-off-by: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05target-ppc: fix invalid mask - cmpl, bctarAvinesh Kumar1-2/+2
cmpl: invalid bit mask should be 0x00400001 bctar: invalid bit mask should be 0x0000E000 Signed-off-by: Avinesh Kumar <avinesku@linux.vnet.ibm.com> Signed-off-by: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05target-ppc: add stxvb16x instructionNikunj A Dadhania2-0/+20
stxvb16x: Store VSX Vector Byte*16 Vector (8-bit elements): +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ |F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7| +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ Store results in following: Little/Big-endian Storage +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ |F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7| +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05target-ppc: add lxvb16x instructionNikunj A Dadhania2-0/+20
lxvb16x: Load VSX Vector Byte*16 Little/Big-endian Storage +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ |F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7| +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ Vector load results in (8-bit elements): +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ |F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7| +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05target-ppc: add stxvh8x instructionNikunj A Dadhania2-0/+32
stxvh8x: Store VSX Vector Halfword*8 Vector (16-bit elements): +------+------+------+------+------+------+------+------+ | 0001 | 1011 | 2021 | 3031 | 4041 | 5051 | 6061 | 7071 | +------+------+------+------+------+------+------+------+ Store results in following: Big-Endian Storage +-------+-------+-------+-------+-------+-------+-------+-------+ | 00 01 | 10 11 | 20 21 | 30 31 | 40 41 | 50 51 | 60 61 | 70 71 | +-------+-------+-------+-------+-------+-------+-------+-------+ Little-Endian Storage +-------+-------+-------+-------+-------+-------+-------+-------+ | 01 00 | 11 10 | 21 20 | 31 30 | 41 40 | 51 50 | 61 60 | 71 70 | +-------+-------+-------+-------+-------+-------+-------+-------+ Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> [dwg: Tweak commit description] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05target-ppc: add lxvh8x instructionNikunj A Dadhania2-0/+50
lxvh8x: Load VSX Vector Halfword*8 Big-Endian Storage +-------+-------+-------+-------+-------+-------+-------+-------+ | 00 01 | 10 11 | 20 21 | 30 31 | 40 41 | 50 51 | 60 61 | 70 71 | +-------+-------+-------+-------+-------+-------+-------+-------+ Little-Endian Storage +-------+-------+-------+-------+-------+-------+-------+-------+ | 01 00 | 11 10 | 21 20 | 31 30 | 41 40 | 51 50 | 61 60 | 71 70 | +-------+-------+-------+-------+-------+-------+-------+-------+ Vector load results in (16-bit elements): +------+------+------+------+------+------+------+------+ | 0001 | 1011 | 2021 | 3031 | 4041 | 5051 | 6061 | 7071 | +------+------+------+------+------+------+------+------+ Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> [dwg: Tweak to commit description] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05target-ppc: improve stxvw4x implementationNikunj A Dadhania1-14/+19
Manipulate data and store 8bytes instead of 4bytes. Vector (32-bit elements): +----------+----------+----------+----------+ | 00112233 | 44556677 | 8899AABB | CCDDEEFF | +----------+----------+----------+----------+ Store results in following: Big-Endian Storage +-------------+-------------+-------------+-------------+ | 00 11 22 33 | 44 55 66 77 | 88 99 AA BB | CC DD EE FF | +-------------+-------------+-------------+-------------+ Little-Endian Storage +-------------+-------------+-------------+-------------+ | 33 22 11 00 | 77 66 55 44 | BB AA 99 88 | FF EE DD CC | +-------------+-------------+-------------+-------------+ Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05target-ppc: improve lxvw4x implementationNikunj A Dadhania1-14/+18
Load 8byte at a time and manipulate. Big-Endian Storage +-------------+-------------+-------------+-------------+ | 00 11 22 33 | 44 55 66 77 | 88 99 AA BB | CC DD EE FF | +-------------+-------------+-------------+-------------+ Little-Endian Storage +-------------+-------------+-------------+-------------+ | 33 22 11 00 | 77 66 55 44 | BB AA 99 88 | FF EE DD CC | +-------------+-------------+-------------+-------------+ Vector load results in (32-bit elements): +----------+----------+----------+----------+ | 00112233 | 44556677 | 8899AABB | CCDDEEFF | +----------+----------+----------+----------+ Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> [dwg: Slight tweak to commit description] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05target-ppc: Implement mtvsrdd instructionRavi Bangoria2-0/+24
mtvsrdd: Move To VSR Double Doubleword Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05target-ppc: Implement mfvsrld instructionRavi Bangoria2-0/+18
mfvsrld: Move From VSR Lower Doubleword Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05ppc: Check the availability of transactional memoryThomas Huth3-1/+17
KVM-PR currently does not support transactional memory, and the implementation in TCG is just a fake. We should not announce TM support in the ibm,pa-features property when running on such a system, so disable it by default and only enable it if the KVM implementation supports it (i.e. recent versions of KVM-HV). These changes are based on some earlier work from Anton Blanchard (thanks!). Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05hw/ppc/spapr: Fix the selection of the processor featuresThomas Huth1-2/+9
The current code uses pa_features_206 for POWERPC_MMU_2_06, and for everything else, it uses pa_features_207. This is bad in some cases because there is also a "degraded" MMU version of ISA 2.06, called POWERPC_MMU_2_06a, which should of course use the flags for 2.06 instead. And there is also the possibility that the user runs the pseries machine with a POWER5+ or even 970 processor. In that case we certainly do not want to set the flags for 2.07, and rather simply skip the setting of the pa-features property instead. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05hw/ppc/spapr: Move code related to "ibm,pa-features" to a separate functionThomas Huth1-30/+36
The function spapr_populate_cpu_dt() has become quite big already, and since we likely have to extend the pa-features property for every new processor generation, it is nicer if we put the related code into a separate function. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05pseries: Add 2.8 machine type, set up compatibility macrosDavid Gibson1-2/+20
Now that 2.7 is released, create the pseries-2.8 machine type and add the boilerplate compatiblity macro stuff. There's nothing new to put into the 2.7 compatiliby properties yet, but we'll need something eventually, so we might as well get it ready now. Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05tests: Test IPv6 and ppc64 in the PXE testerThomas Huth3-7/+25
The firmware of the pseries machine, SLOF, is able to load files via IPv6 networking, too. So to test both, network bootloading on ppc64 and IPv6 (via Slirp) , let's add some PXE tests for this environment, too. Since we can not use the normal x86 boot sector for network boot loading, we use a simple Forth script on ppc64 instead. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05spapr_vscsi: fix build error introduced by f19661c8Felipe Franciosi2-2/+2
A typo introduced in f19661c8 prevents qemu from building when configured with --enable-trace-backend=dtrace. Signed-off-by: Felipe Franciosi <felipe@nutanix.com> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-04Merge remote-tracking branch 'remotes/dgilbert/tags/pull-hmp-20161004' into ↵Peter Maydell1-1/+2
staging HMP pull Just Wanpeng's pull request this time, but this pull is as much about me checking out my process. # gpg: Signature made Tue 04 Oct 2016 18:24:10 BST # gpg: using RSA key 0x0516331EBC5BFDE7 # gpg: Good signature from "Dr. David Alan Gilbert (RH2) <dgilbert@redhat.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 45F5 C71B 4A0C B7FB 977A 9FA9 0516 331E BC5B FDE7 * remotes/dgilbert/tags/pull-hmp-20161004: hmp: fix qemu crash due to ioapic state dump w/ split irqchip Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04hmp: fix qemu crash due to ioapic state dump w/ split irqchipWanpeng Li1-1/+2
The qemu will crash when info ioapic through hmp if irqchip is split. Below message is splat: KVM_GET_IRQCHIP failed: Unknown error -6 This patch fix it by dumping the ioapic state from the qemu emulated ioapic if irqchip is split. Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Richard Henderson <rth@twiddle.net> Cc: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Wanpeng Li <wanpeng.li@hotmail.com> Message-Id: <1474602456-3232-1-git-send-email-wanpeng.li@hotmail.com> Reviewed-by: Peter Xu <peterx@redhat.com> Message-ID: <20160923090824.GF15411@pxdev.xzpeter.org> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2016-10-04Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into stagingPeter Maydell21-191/+342
Block layer patches # gpg: Signature made Thu 29 Sep 2016 14:11:30 BST # gpg: using RSA key 0x7F09B272C88F2FD6 # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * remotes/kevin/tags/for-upstream: oslib-posix: add a configure switch to debug stack usage coroutine-sigaltstack: use helper for allocating stack memory coroutine-ucontext: use helper for allocating stack memory coroutine: add a macro for the coroutine stack size coroutine-sigaltstack: rename coroutine struct appropriately oslib-posix: add helpers for stack alloc and free block: Remove qemu_root_bds_opts block: Move 'discard' option to bdrv_open_common() block: Use 'detect-zeroes' option for 'blockdev-change-medium' block: Parse 'detect-zeroes' in bdrv_open_common() block/qapi: Move 'aio' option to file driver block/qapi: Use separate options type for curl driver block: Drop aio/cache consistency check from qmp_blockdev_add() block: Fix error path in qmp_blockdev_change_medium() block-backend: remove blk_flush_all qemu: use bdrv_flush_all for vm_stop et al block: reintroduce bdrv_flush_all Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04Merge remote-tracking branch ↵Peter Maydell39-316/+2027
'remotes/pmaydell/tags/pull-target-arm-20161004' into staging target-arm queue: * Netduino 2 improvements (SPI, ADC devices) * fix some Mainstone key mappings * vmstateify tsc210x, tsc2005 * virt: add 2.8 machine type * virt: support in-kernel GICv3 ITS * generic-loader device * A64: fix iss_sf decoding in disas_ld_lit * correctly handle 'sub pc, pc, 1' for ARMv6 # gpg: Signature made Tue 04 Oct 2016 13:41:34 BST # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20161004: (27 commits) target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6 target-arm: A64: Fix decoding of iss_sf in disas_ld_lit cadence_gem: Fix priority queue out of bounds access docs: Add a generic loader explanation document generic-loader: Add a generic loader ARM: Virt: ACPI: Add GIC ITS description in ACPI MADT table ACPI: Add GIC Interrupt Translation Service Structure definition arm/virt: Add ITS to the virt board hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulation kvm-all: Pass requester ID to MSI routing functions target-arm: move gicv3_class_name from machine to kvm_arm.h hw/intc/arm_gicv3_its: Implement ITS base class hw/intc/arm_gic(v3)_kvm: Initialize gsi routing hw/arm/virt: add 2.8 machine type vmstateify tsc210x vmstateify tsc2005 hw/arm: Fix Integrator/CM initialization mainstone: Add mapping for dot, slash and backspace. mainstone: Fix incorrect key mapping for Enter key. MAINTAINERS: Add Alistair to the maintainers list ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6Peter Maydell1-1/+6
In the ARM v6 architecture, 'sub pc, pc, 1' is not an interworking branch, so the computed new value is written to r15 as a normal value. The architecture says that in this case, bits [1:0] of the value written must be ignored if we are in ARM mode (or bit [0] ignored if in Thumb mode); this is a change from the ARMv4/v5 specification that behaviour is UNPREDICTABLE. Use the correct mask on the PC value when doing a non-interworking store to PC. A popular library used on RaspberryPi uses this instruction as part of a trick to determine whether it is running on ARMv6 or ARMv7, and we were mishandling the sequence. Fixes bug: https://bugs.launchpad.net/bugs/1625295 Reported-by: <stu.axon@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1474380941-4730-1-git-send-email-peter.maydell@linaro.org
2016-10-04target-arm: A64: Fix decoding of iss_sf in disas_ld_litEdgar E. Iglesias1-1/+1
Fix the decoding of iss_sf in disas_ld_lit. The SF (Sixty-Four) field in the ISS (Instruction Specific Syndrome) is a bit that specifies the width of the register that the instruction loads to. If cleared it specifies 32 bits. If set it specifies 64 bits. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1475230780-8669-1-git-send-email-edgar.iglesias@gmail.com [PMM: tweaked phrasing per on-list discussion] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04cadence_gem: Fix priority queue out of bounds accessAlistair Francis1-18/+4
There was an error with some of the register implementation assuming there are 16 priority queues supported when the IP only supports 8. This patch corrects the registers to only support 8 queues. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reported-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 33bf2d28326d22875602234b8b15cf56fb678333.1474911607.git.alistair.francis@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04docs: Add a generic loader explanation documentAlistair Francis1-0/+84
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 9d991a2df990cf55e2630410a5a03ea48930af5d.1475195078.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04generic-loader: Add a generic loaderAlistair Francis4-0/+265
Add a generic loader to QEMU which can be used to load images or set memory values. Internally inside QEMU this is a device. It is a strange device that provides no hardware interface but allows QEMU to monkey patch memory specified when it is created. To be able to do this it has a reset callback that does the memory operations. This device allows the user to monkey patch memory. To be able to do this it needs a backend to manage the datas, the same as other memory-related devices. In this case as the backend is so trivial we have merged it with the frontend instead of creating and maintaining a seperate backend. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Markus Armbruster <armbru@redhat.com> Message-id: 10f2a9dce5e5e11b6c6d959415b0ad6ee22bcba5.1475195078.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04ARM: Virt: ACPI: Add GIC ITS description in ACPI MADT tableShannon Zhao1-0/+12
If GIC ITS is supported, add description in ACPI MADT table, then guest could use ITS when booting with ACPI. Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Eric Auger <eric.auger@redhat.com> Message-id: 1474616617-366-9-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04ACPI: Add GIC Interrupt Translation Service Structure definitionShannon Zhao1-1/+12
ACPI Spec 6.0 introduces GIC Interrupt Translation Service Structure. Here we add the definition of the Structure. Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Eric Auger <eric.auger@redhat.com> Message-id: 1474616617-366-8-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04arm/virt: Add ITS to the virt boardPavel Fedin1-6/+41
If supported by the configuration, ITS will be added automatically. This patch also renames v2m_phandle to msi_phandle because it's now used by both MSI implementations. Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1474616617-366-7-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulationPavel Fedin2-0/+122
The ITS control frame is in-kernel emulated while accesses to the GITS_TRANSLATER are mediated through the KVM_SIGNAL_MSI ioctl (MSI direct MSI injection advertised by the CAP_SIGNAL_MSI capability) the kvm_gsi_direct_mapping is explicitly set to false to emphasize the difference with GICv2M. Direct mapping cannot work with ITS since the content of the MSI data is not the target interrupt ID but an eventd id. GSI routing is advertised (kvm_gsi_routing_allowed) as well as msi/irqfd signaling (kvm_msi_via_irqfd_allowed). The MSI frame (GITS_TRANSLATER) absolute GPA is computed on first kvm_its_send_msi() call. It is then passed through KVM_SIGNAL_MSI ioctl. Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Message-id: 1474616617-366-6-git-send-email-eric.auger@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04kvm-all: Pass requester ID to MSI routing functionsPavel Fedin3-0/+19
Introduce global kvm_msi_use_devid flag plus associated kvm_msi_devid_required() macro. Passes the device ID, if needed, while building the MSI route entry. Device IDs are required by the ARM GICv3 ITS (IRQ remapping function is based on this information). Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Message-id: 1474616617-366-5-git-send-email-eric.auger@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04target-arm: move gicv3_class_name from machine to kvm_arm.hEric Auger2-16/+15
Machine.c contains code related to migration. Let's move gicv3_class_name to kvm_arm.h instead. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1474616617-366-4-git-send-email-eric.auger@redhat.com Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04hw/intc/arm_gicv3_its: Implement ITS base classPavel Fedin4-0/+246
This is the basic skeleton for both KVM and software-emulated ITS. Since we already prepare status structure, we also introduce complete VMState description. But, because we currently have no migratable implementations, we also set unmigratable flag. Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1474616617-366-3-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04hw/intc/arm_gic(v3)_kvm: Initialize gsi routingEric Auger2-0/+25
Advertise gsi routing and set up irqchip routing entries for GIC SPIs. This is not mandated as long as MSI routing is not used (because the kernel sets a default irqchip routing table). However once MSI routing gets used (for VIRTIO-PCI vhost for example), the first call to KVM_SET_GSI_ROUTING overrides the kernel default irqchip table. If no routing entry exists for the GSI, any IRQFD signaling for this GSI will fail. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1474616617-366-2-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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