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2013-03-22mmu-hash*: Make find_pte{32, 64} do more of the job of finding ptesDavid Gibson2-147/+92
find_pte{32,64}() are not particularly well named. They only "find" a PTE within a given PTE group, and they also do permissions checking and other things. This patch makes it somewhat close to matching the name, by folding the search of both primary and secondary hash bucket into it, along with the various address bit shuffling to determine the right hash buckets. In the 32-bit case we also remove the code for splitting large pages into 4k pieces for the qemu tlb, since no 32-bit hash MMUs support multiple page sizes. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22mmu-hash*: Separate PTEG searching from permissions checkingDavid Gibson4-67/+77
find_pte{32,64{() do several things. First they search through a PTEG ooking for a PTE matching our virtual address. Then they do permissions checking and other processing on that PTE. This patch separates the search by VA out from the rest. The search is combined with the pte{32,64}_match() functions into new ppc_has{32,64}_pteg_search() functions. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22mmu-hash*: Don't keep looking for PTEs after we find a matchDavid Gibson2-122/+60
BEHAVIOUR CHANGE The ppc hash mmu hashes each virtual address to a primary and secondary possible hash bucket (aka PTE group or PTEG) each with 8 PTEs. Then we need a linear search through the PTEs to find the correct one for the virtual address we're translating. It is a programming error for the guest to insert multiple PTEs mapping the same virtual address into a PTEG - in this case the ppc architecture says the MMU can either act as if just one was present, or give a machine check. Currently our code takes the first matching PTE in a PTEG if it finds a successful translation. But if a matching PTE is found, but permission bits don't allow the access, we keep looking through the PTEG, checking that any other matching PTEs contain an identical translation. That behaviour is perhaps not exactly wrong, but it's certainly not useful. This patch changes it to always just find the first matching PTE in a PTEG. In addition, if we get a permissions problem on the primary PTEG, we then search the secondary PTEG. This is incorrect - a permission denying PTE in the primary PTEG should not be overwritten by an access granting PTE in the secondary (although again, it would be a programming error for the guest to set up such a situation anyway). So additionally we update the code to only search the secondary PTEG if no matching PTE is found in the primary at all. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22mmu-hash*: Cleanup segment-level NX checkDavid Gibson2-83/+83
On the ppc hash mmus, no-execute can be set at the segment level (on more recent 64-bit hash mmus it can also be set at the page level). This patch separates out this check to make it clearer what is going on, and avoiding excessive indentation of the remaining translation code. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22mmu-hash32: Split direct store segment handling into a helperDavid Gibson1-56/+61
This further separates the unusual case handling of direct store segments from the main translation path by moving its logic into a helper function, with some tiny cleanups along the way. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22mmu-hash32: Split out handling of direct store segmentsDavid Gibson1-78/+78
At present a large chunk of ppc_hash32_translate() is taken up with an ugly if selecting between direct store segments (hardly ever used) and normal paged segments. This patch clarifies the flow of code by handling direct store segments immediately then returning, leaving the straight line code to describe the normal MMU path. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22mmu-hash*: Combine ppc_hash{32, 64}_get_physical_address and get_segment{32, ↵David Gibson2-51/+35
64}() After previous work, ppc_hash{32,64}_get_physical_address() are almost trivial wrappers around get_segment{32,64}() which does nearly all the work of translating an address according to the hash mmu model. Therefore combine the two functions into one, under the better name of ppc_hash{32,64}_translate(). Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22mmu-hash*: Remove eaddr field from mmu_ctx_hash{32, 64}David Gibson2-14/+10
The eaddr field of mmu_ctx_hash{32,64} is effectively just used to pass the effective address from get_segment{32,64}() to find_pte{32,64}(). Just pass it as a normal parameter instead. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22mmu-hash64: Remove nx from mmu_ctx_hash64David Gibson1-8/+8
The nx field in mmu_ctx_hash64 is used in two different functions. But its used for slightly different things in each place, and the value is never propagated between them. In other words, it might as well be two local variables. This patch makes it so. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22mmu-hash*: Reduce use of access_typeDavid Gibson2-87/+66
In ppc env->access_type is updated by e.g. integer load/stores with ACCESS_INT floating point load/stores with ACCESS_FLOAT and so forth. In hash mmu fault paths it can also b set to ACCESS_CODE for instruction fetch accesses. But the only place which uses anything more of the access_type than whether it is instruction fetch or data access is the direct store segment handling. Instruction versus data access can be more simply determined from the rw value passed down from the top. This changes the code to use rw in preference to checking access_type. For the 32-bit case there is a small amount of code (for direct store segments) that still needs the full access type. Instead of passing it all the way down the stack, we retrieve it from the env structure, which is where it came anyway, before this patch. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22mmu-hash*: Add hash pte load/store helpersDavid Gibson5-47/+94
On real hardware the ppc hash page table is stored in memory; accordingly our mmu emulation code can read a hash page table in guest memory. But, when paravirtualized under PAPR, the real hash page table is in host memory, accessible to the guest only via hypercalls. We model this by also allowing the MMU emulation code to access a specially allocated hash page table outside the guest's memory image. At present these two options are implemented with some ugly conditionals at each access point in the mmu emulation code. In the implementation of the PAPR hypercalls, we assume the external hash table. This patch cleans things up by adding helpers to load and store from the hash table for both 32-bit and 64-bit hash mmus. The 64-bit versions handle both the in-guest-memory and outside guest memory cases. The 32-bit versions only handle the in-guest-memory case since no 32-bit systems can have an external hash table at present. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22mmu-hash*: Add header file for definitionsDavid Gibson7-141/+190
Currently cpu.h contains a number of definitions relating to the 64-bit hash MMU. Some are used in the MMU emulation code, but some are only used in the spapr MMU management hcall implementations. This patch moves these definitions (except for a few that are needed more widely) into mmu-hash64.h header, shared between the MMU emulation code and the spapr hcall code. The MMU emulation code is also updated to actually use a number of those definitions in place of hard coded constants. Similarly, we add new analogous definitions to mmu-hash32.h and use those in place of many hard-coded constants in mmu-hash32.c Signed-off-by: David Gibson <david@gibson.dropbear.id.au> [agraf: fix 32-bit hosts] Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: mmu_ctx_t should not be a global typeDavid Gibson4-29/+50
mmu_ctx_t is currently defined in cpu.h. However it is used for temporary information relating to mmu translation, and is only used in mmu_helper.c and (now) mmu-hash{32,64}.c. Furthermore it contains information which should be specific to particular MMU types. Therefore, move its definition to mmu_helper.c. mmu-hash{32,64}.c are converted to use new data types private to the relevant MMUs (identical to mmu_ctx_t for now, but that will change in future patches). Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Disentangle BAT code for 32-bit hash MMUsDavid Gibson3-38/+142
The functions for looking up BATs (Block Address Translation - essentially a level 0 TLB) are shared between the classic 32-bit hash MMUs and the 6xx style software loaded TLB implementations. This patch splits out a copy for the 32-bit hash MMUs, to facilitate cleaning it up. The remaining version is left, but cleaned up slightly to no longer deal with PowerPC 601 peculiarities (601 has a hash MMU). Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Don't share get_pteg_offset() between 32 and 64-bitDavid Gibson5-11/+10
The get_pteg_offset() helper function is currently shared between 32-bit and 64-bit hash mmus, taking a parameter for the hash pte size. In the 64-bit paths, it's only called in one place, and it's a trivial calculation. This patch, therefore, open codes it for 64-bit. The remaining version, which is used in two places is made 32-bit only and moved to mmu-hash32.c. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Disentangle hash mmu helper functionsDavid Gibson4-16/+193
The newly separated paths for hash mmus rely on several helper functions which are still shared with 32-bit hash mmus: pp_check(), check_prot() and pte_update_flags(). While these don't have ugly ifdefs on the mmu type, they're not very well thought out, so sharing them impedes cleaning up the hash mmu paths. For now, put near-duplicate versions into mmu-hash64.c and mmu-hash32.c, leaving the old version in mmu_helper.c for 6xx software loaded tlb implementations. The hash 32 and software loaded implementations are simplfied slightly, using the fact that no 32-bit CPUs implement the 3rd page protection bit. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Disentangle hash mmu versions of cpu_get_phys_page_debug()David Gibson5-21/+48
cpu_get_phys_page_debug() is a trivial wrapper around get_physical_address(). But even the signature of get_physical_address() has some things we'd like to clean up on a per-mmu basis, so this patch moves the test on mmu model out to cpu_get_phys_page_debug(), moving the version for 64-bit hash MMUs out to mmu-hash64.c and the version for 32-bit hash MMUs to mmu-hash32.c Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Disentangle hash mmu paths for cpu_ppc_handle_mmu_faultDavid Gibson5-41/+231
cpu_ppc_handle_mmu_fault() calls get_physical_address() (whose behaviour depends on MMU type) then, if that fails, issues an appropriate exception - which again has a number of dependencies on MMU type. This patch starts converting cpu_ppc_handle_mmu_fault() to have a single switch on MMU type, calling MMU specific fault handler functions which deal with both translation and exception delivery appropriately for the MMU type. We convert 32-bit and 64-bit hash MMUs to this new model, but the existing code is left in place for other MMU types for now. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Disentangle get_physical_address() pathsDavid Gibson6-46/+58
Depending on the MSR state, for 64-bit hash MMUs, get_physical_address can either call check_physical (which has further tests for mmu type) or get_segment64. Similarly for 32-bit hash MMUs we can either call check_physucal or get_bat() and get_segment32(). This patch splits off the whole get_physical_addresss() path for hash MMUs into 32-bit and 64-bit versions, handling real mode correctly for such MMUs without going to check_physical and rechecking the mmu type. Correspondingly, the hash MMU specific paths in check_physical() are removed. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Rework get_physical_address()David Gibson1-46/+52
Currently get_physical_address() first checks to see if translation is enabled in the MSR, then in the translation on case switches on the mmu type. Except that for BookE MMUs, translation is always on, and so it has to switch in the "translation off" case as well and do the same thing as the translation on path for those MMUs. Plus, even translation off doesn't behave exactly the same on the various MMU types so there are further mmu type checks in the "translation off" path. As a first step to cleaning this up, this patch moves the switch on mmu type to the top level, then makes the translation on/off check just for those mmu types where it is meaningful. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Disentangle get_segment()David Gibson5-111/+280
The poorly named get_segment() function handles most of the address translation logic for hash-based MMUs. It has many ugly conditionals on whether the MMU is 32-bit or 64-bit. This patch splits the function into 32 and 64-bit versions, using the switch on mmu_type that's already in the caller (get_physical_address()) to select the right one. Most of the original function remains in mmu_helper.c to support the 6xx software loaded TLB implementations (cleaning those up is a project for another day). Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Disentangle find_pte()David Gibson6-122/+164
32-bit and 64-bit hash MMU implementations currently share a find_pte function. This results in a whole bunch of ugly conditionals in the shared function, and not all that much actually shared code. This patch separates out the 32-bit and 64-bit versions, putting then in mmu-hash64.c and mmu-has32.c, and removes the conditionals from both versions. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Disentangle pte_check()David Gibson7-56/+179
Currently support for both 32-bit and 64-bit hash MMUs share an implementation of pte_check. But there are enough differences that this means the shared function has several very ugly conditionals on "is_64b". This patch cleans things up by separating out the 64-bit version (putting it into mmu-hash64.c) and the 32-bit hash version (putting it in mmu-hash32.c). Another copy remains in mmu_helper.c, which is used for the 6xx software loaded TLB paths. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Move SLB handling into a mmu-hash64.cDavid Gibson5-199/+232
As a first step to disentangling the handling for 64-bit hash MMUs from the rest, we move the code handling the Segment Lookaside Buffer (SLB) (which only exists on 64-bit hash MMUs) into a new mmu-hash64.c file. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Remove address check for loggingDavid Gibson1-6/+4
One LOG_MMU statement in mmu_helper.c has an odd check on the effective address being translated. I can see no reason for this; I suspect it was a debugging hack from long ago. This patch removes it. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Trivial cleanups in mmu_helper.cDavid Gibson2-11/+3
This removes the never-used pte64_invalidate() function, and makes ppcmas_tlb_check() static, since it's only used within that file. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Remove vestigial PowerPC 620 supportDavid Gibson9-339/+8
The PowerPC 620 was the very first 64-bit PowerPC implementation, but hardly anyone ever actually used the chips. qemu notionally supports the 620, but since we don't actually have code to implement the segment table, the support is broken (quite likely in other ways too). This patch, therefore, removes all remaining pieces of 620 support, to stop it cluttering up the platforms we actually care about. This includes removing support for the ASR register, used only on segment table based machines. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22PPC/GDB: handle read and write of fpscrFabien Chouteau4-2/+10
Although the support of this register may be uncomplete, there are no reason to prevent the debugger from reading or writing it. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22pseries: Move XICS initialization before cpu initializationDavid Gibson3-38/+34
Currently, the pseries machine initializes the cpus, then the XICS interrupt controller. However, to support the upcoming in-kernel XICS implementation we will need to initialize the irq controller before the vcpus. This patch makes the necesssary rearrangement. This means the xics init code can no longer auto-detect the number of cpus ("interrupt servers" in XICS terminology) and so we must pass that in explicitly from the platform code. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Ben Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Remove CONFIG_PSERIES dependency in kvm.cDavid Gibson1-1/+1
target-ppc/kvm.c has an #ifdef on CONFIG_PSERIES, for the handling of KVM exits due to a PAPR hypercall from the guest. However, since commit e4c8b28cde12d01ada8fe869567dc5717a2dfcb7 "ppc: express FDT dependency of pSeries and e500 boards via default-configs/", this hasn't worked properly. That patch altered the configuration setup so that although CONFIG_PSERIES is visible from the Makefiles, it is not visible from C files. This broke the pseries machine when KVM is in use. This patch makes a quick and dirty fix, by removing the CONFIG_PSERIES dependency, replacing it with TARGET_PPC64 (since removing it entirely leads to type mismatch errors). Technically this breaks the build when configured with --disable-fdt, since that disables CONFIG_PSERIES on TARGET_PPC64. However, it turns out the build was already broken in that case, so this fixes pseries kvm without breaking anything extra. I'm looking into how to fix that build breakage, but I don't think that need delay applying this patch. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22pseries: Remove "busname" property for PCI host bridgeDavid Gibson3-12/+24
Currently the "spapr-pci-host-bridge" device has a "busname" property which can be used to override the default assignment of qbus names for the bus subordinate to the PHB. We use that for the default primary PCI bus, to make libvirt happy, which expects there to be a bus named simply "pci". The default qdev core logic would name the bus "pci.0", and the pseries code would otherwise name it "pci@800000020000000" which is the name it is given in the device tree based on its BUID. The "busname" property is rather clunky though, so this patch simplifies things by just using a special case hack for the default PHB, setting busname to "pci" when index=0. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22pseries: Fix breakage in CPU QOM conversionDavid Gibson1-1/+1
Commit 259186a7d2f7184efc96ae99bc5658e6159f53ad "cpu: Move halted and interrupt_request fields to CPUState" broke the pseries machine. That's because it uses CPU() instead of ENV_GET_CPU() to convert from the global first_cpu pointer (still a CPUArchState) to a CPUState. This patch fixes the breakage. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22serial: Fix debug format stringsKevin Wolf1-2/+2
This fixes the build of hw/serial.c with DEBUG_SERIAL enabled. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-03-22Fix typos and misspellingsPeter Maydell11-15/+15
Fix various typos and misspellings. The bulk of these were found with codespell. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-03-22Advertise --libdir in configure --help outputDoug Goldstein1-0/+1
The configure script allows you to supply a libdir via --libdir but was not advertising this in --help. Signed-off-by: Doug Goldstein <cardoe@cardoe.com> CC: qemu-trivial@nongnu.org Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-03-22memory: fix a bug of detection of memory region collisionHu Tao1-1/+1
The collision reports before and after this patch are: before: warning: subregion collision cfc/4 (pci-conf-data) vs cf8/4 (pci-conf-idx) warning: subregion collision 8000000/f8000000 (pci-hole) vs 0/8000000 (ram-below-4g) warning: subregion collision 100000000/4000000000000000 (pci-hole64) vs 8000000/f8000000 (pci-hole) warning: subregion collision 4d1/1 (kvm-elcr) vs 4d0/1 (kvm-elcr) warning: subregion collision fec00000/1000 (kvm-ioapic) vs 8000000/f8000000 (pci-hole) warning: subregion collision 80/1 (ioport80) vs 7e/2 (kvmvapic) warning: subregion collision fed00000/400 (hpet) vs 8000000/f8000000 (pci-hole) warning: subregion collision 81/3 (dma-page) vs 80/1 (ioport80) warning: subregion collision 8/8 (dma-cont) vs 0/8 (dma-chan) warning: subregion collision d0/10 (dma-cont) vs c0/10 (dma-chan) warning: subregion collision 0/80 (ich9-pm) vs 8/8 (dma-cont) warning: subregion collision 0/80 (ich9-pm) vs 0/8 (dma-chan) warning: subregion collision 0/80 (ich9-pm) vs 64/1 (i8042-cmd) warning: subregion collision 0/80 (ich9-pm) vs 60/1 (i8042-data) warning: subregion collision 0/80 (ich9-pm) vs 61/1 (elcr) warning: subregion collision 0/80 (ich9-pm) vs 40/4 (kvm-pit) warning: subregion collision 0/80 (ich9-pm) vs 70/2 (rtc) warning: subregion collision 0/80 (ich9-pm) vs 20/2 (kvm-pic) warning: subregion collision 0/80 (ich9-pm) vs 7e/2 (kvmvapic) warning: subregion collision 4/2 (acpi-cnt) vs 0/4 (acpi-evt) warning: subregion collision 30/8 (apci-smi) vs 20/10 (apci-gpe0) warning: subregion collision b0000000/10000000 (pcie-mmcfg) vs 8000000/f8000000 (pci-hole) after: warning: subregion collision fec00000/1000 (kvm-ioapic) vs 8000000/f8000000 (pci-hole) warning: subregion collision fed00000/400 (hpet) vs 8000000/f8000000 (pci-hole) warning: subregion collision 0/80 (ich9-pm) vs 8/8 (dma-cont) warning: subregion collision 0/80 (ich9-pm) vs 0/8 (dma-chan) warning: subregion collision 0/80 (ich9-pm) vs 64/1 (i8042-cmd) warning: subregion collision 0/80 (ich9-pm) vs 60/1 (i8042-data) warning: subregion collision 0/80 (ich9-pm) vs 61/1 (elcr) warning: subregion collision 0/80 (ich9-pm) vs 40/4 (kvm-pit) warning: subregion collision 0/80 (ich9-pm) vs 70/2 (rtc) warning: subregion collision 0/80 (ich9-pm) vs 20/2 (kvm-pic) warning: subregion collision 0/80 (ich9-pm) vs 7e/2 (kvmvapic) warning: subregion collision b0000000/10000000 (pcie-mmcfg) vs 8000000/f8000000 (pci-hole) Signed-off-by: Hu Tao <hutao@cn.fujitsu.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-03-22MinGW: Replace setsockopt by qemu_setsocketoptStefan Weil8-27/+26
Instead of adding missing type casts which are needed by MinGW for the 4th argument, the patch uses qemu_setsockopt which was invented for this purpose. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-03-20virtio-ccw, s390-virtio: Use generic virtio-blk macro.Cornelia Huck2-14/+2
Now that virtio-ccw and s390-virtio define all common properties for virtio-blk, we can switch to using the generic DEFINE_VIRTIO_BLK_PROPERTIES macro. CC: Alexander Graf <agraf@suse.de> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2013-03-20s390-virtio, virtio-ccw: Add config_wce for virtio-blk.Cornelia Huck2-0/+2
There's no reason why we wouldn't want to make the cache mode configurable. Acked-by: Alexander Graf <agraf@suse.de> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2013-03-20virtio-ccw: Add missing blk chs properties.Cornelia Huck1-0/+1
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2013-03-19microblaze: Ignore non-cpu accesses to unmapped areasEdgar E. Iglesias1-1/+1
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2013-03-19Merge remote-tracking branch 'kraxel/ipxe.2' into stagingAnthony Liguori14-7/+73
# By Gerd Hoffmann # Via Gerd Hoffmann * kraxel/ipxe.2: Switch to efi-enabled nic roms by default Add efi rom binaries Add Makefile rules to build nic rom binaries with efi support Update ipxe submodule to latest master Add Makefile rules to build nic rom binaries
2013-03-19add a boot option to do strict bootAmos Kong2-3/+30
Seabios already added a new device type to halt booting. Qemu can add "HALT" at the end of bootindex string, then seabios will halt booting after trying to boot from all selected devices. This patch added a new boot option to configure if boot from un-selected devices. This option only effects when boot priority is changed by bootindex options, the old style(-boot order=..) will still try to boot from un-selected devices. v2: add HALT entry in get_boot_devices_list() v3: rebase to latest qemu upstream Signed-off-by: Amos Kong <akong@redhat.com> Message-id: 1363674207-31496-1-git-send-email-akong@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-03-19ui/cocoa.m: Fix compile failures introduced by recent console changesPeter Maydell1-3/+6
Fix various compilation failures introduced by the recent console changes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1363638501-29603-1-git-send-email-peter.maydell@linaro.org Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-03-19Merge remote-tracking branch 'kwolf/for-anthony' into stagingAnthony Liguori8-8/+92
# By Stefan Hajnoczi (2) and others # Via Kevin Wolf * kwolf/for-anthony: virtio-blk: Do not segfault fault if failed to initialize dataplane qemu-iotests: add 052 BDRV_O_SNAPSHOT test block: fix BDRV_O_SNAPSHOT protocol detection qcow2: Fix segfault in qcow2_invalidate_cache sheepdog: show error message for halt status
2013-03-19char: Fix return type of qemu_chr_fe_add_watch()Kevin Wolf2-4/+4
qemu_chr_fe_add_watch() can return negative errors, therefore it must not have an unsigned return type. For consistency with other qemu_chr_fe_* functions, this uses a standard C int instead of glib types. In situations where qemu_chr_fe_add_watch() is falsely assumed to have succeeded, the serial ports would go into a state where it never becomes ready for transmitting more data; this is fixed by this patch. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-03-19fix monitorGerd Hoffmann1-2/+21
chardev flow control broke monitor, fix it by adding watch support. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-03-19virtio-blk: Do not segfault fault if failed to initialize dataplaneDunrong Huang1-1/+1
$ ~/usr/bin/qemu-system-x86_64 -enable-kvm -m 1024 -drive if=none,id=drive0,cache=none,aio=native,format=raw,file=/root/Image/centos-6.4.raw -device virtio-blk-pci,drive=drive0,scsi=off,x-data-plane=on,config-wce=on # make dataplane fail to initialize qemu-system-x86_64: -device virtio-blk-pci,drive=drive0,scsi=off,x-data-plane=on,config-wce=on: device is incompatible with x-data-plane, use config-wce=off *** glibc detected *** /root/usr/bin/qemu-system-x86_64: free(): invalid pointer: 0x00007f001fef12f8 *** ======= Backtrace: ========= /lib64/libc.so.6(+0x7d776)[0x7f00153a5776] /root/usr/bin/qemu-system-x86_64(+0x2c34ec)[0x7f001cf5b4ec] /root/usr/bin/qemu-system-x86_64(+0x342f9a)[0x7f001cfdaf9a] /root/usr/bin/qemu-system-x86_64(+0x33694e)[0x7f001cfce94e] .................... (gdb) bt #0 0x00007f3bf3a12015 in raise () from /lib64/libc.so.6 #1 0x00007f3bf3a1348b in abort () from /lib64/libc.so.6 #2 0x00007f3bf3a51a4e in __libc_message () from /lib64/libc.so.6 #3 0x00007f3bf3a57776 in malloc_printerr () from /lib64/libc.so.6 #4 0x00007f3bfb60d4ec in free_and_trace (mem=0x7f3bfe0129f8) at vl.c:2786 #5 0x00007f3bfb68cf9a in virtio_cleanup (vdev=0x7f3bfe0129f8) at /root/Develop/QEMU/qemu/hw/virtio.c:900 #6 0x00007f3bfb68094e in virtio_blk_device_init (vdev=0x7f3bfe0129f8) at /root/Develop/QEMU/qemu/hw/virtio-blk.c:666 #7 0x00007f3bfb68dadf in virtio_device_init (qdev=0x7f3bfe0129f8) at /root/Develop/QEMU/qemu/hw/virtio.c:1092 #8 0x00007f3bfb50da46 in device_realize (dev=0x7f3bfe0129f8, err=0x7fff479c9258) at hw/qdev.c:176 ............................. In virtio_blk_device_init(), the memory which vdev point to is a static member of "struct VirtIOBlkPCI", not heap memory, and it does not get freed. So we shoule use virtio_common_cleanup() to clean this VirtIODevice rather than virtio_cleanup(), which attempts to free the vdev. This error was introduced by commit 05ff686536f408ba6e8426b1b54d25bd3379fda2 recently. Signed-off-by: Dunrong Huang <huangdr@cloud-times.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2013-03-19qemu-iotests: add 052 BDRV_O_SNAPSHOT testStefan Hajnoczi3-0/+75
Check that writes to an image opened with BDRV_O_SNAPSHOT do not modify the underlying image file. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2013-03-19block: fix BDRV_O_SNAPSHOT protocol detectionStefan Hajnoczi1-5/+1
realpath(3) is used to get an absolute path to the image file when creating a -drive snapshot=on temporary qcow2. This does not work for protocols since their filenames ("proto:foo:...") do not correspond to file system paths. Commit 7c96d46ec245d73fd76726588409f9abe4bd5dc1 ("Let snapshot work with protocols") skipped realpath(3) for protocols. Later on the "raw" format was introduced and broke the check. Use path_has_protocol(filename) to decide if this image uses a protocol or a filename. Reported-by: Richard Jones <rjones@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
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