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2014-10-24MAINTAINERS: add myself as MIPS guest cores co-maintainerLeon Alrae1-1/+2
Add myself to the maintainer list for MIPS guest cores and update the status from "Odd Fixes" to "Maintained". Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Acked-by: Aurelien Jarno <aurelien@aurel32.net> Message-id: 1413459487-13658-1-git-send-email-leon.alrae@imgtec.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24target-mips: add ULL suffix in bitswap to avoid compiler warningLeon Alrae1-6/+6
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Message-id: 1413982829-27225-1-git-send-email-leon.alrae@imgtec.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24Merge remote-tracking branch ↵Peter Maydell39-591/+1395
'remotes/pmaydell/tags/pull-target-arm-20141024' into staging target-arm queue: * remove pointless 'info pcmcia' and a lot of now-dead code * register ARM cpu reset handlers even if not using -kernel * update to libvixl 1.6 * various minor code cleanups * support PSCI under TCG ('virt' machine can now be shut down, SMP configurations work) * correct the sense of the AArch64 DCZID DZP bit * report a valid L1Ip field in CTR_EL0 for CPU type "any" * correctly UNDEF writes to FPINST/FPINST2 from EL0 * more preparatory code refactoring for EL2/EL3 support # gpg: Signature made Fri 24 Oct 2014 12:35:52 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20141024: (23 commits) target-arm: A32: Emulate the SMC instruction target-arm: make arm_current_el() return EL3 target-arm: rename arm_current_pl to arm_current_el target-arm: reject switching to monitor mode target-arm: add arm_is_secure() function target-arm: increase arrays of registers R13 & R14 target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0 target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any" target-arm: Correct sense of the DCZID DZP bit arm/virt: enable PSCI emulation support for system emulation target-arm: add emulation of PSCI calls for system emulation target-arm: Add support for A32 and T32 HVC and SMC insns target-arm: Handle SMC/HVC undef-if-no-ELx in pre_* helpers target-arm: add missing PSCI constants needed for PSCI emulation target-arm: do not set do_interrupt handlers for ARM and AArch64 user modes target-arm: add powered off cpu state omap_gpmc.c: Remove duplicate assignment disas/libvixl/a64/instructions-a64.h: Remove unused constants arm_gic: remove unused parameter. disas/libvixl: Update to libvixl 1.6 ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24target-arm: A32: Emulate the SMC instructionFabian Aggeler2-2/+12
Implements SMC instruction in AArch32 using the A32 syndrome. When executing SMC instruction from monitor CPU mode SCR.NS bit is reset. Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Message-id: 1413910544-20150-7-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24target-arm: make arm_current_el() return EL3Fabian Aggeler1-9/+20
Make arm_current_el() return EL3 for secure PL1 and monitor mode. Increase MMU modes since mmu_index is directly inferred from arm_ current_el(). Change assertion in arm_el_is_aa64() to allow EL3. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1413910544-20150-6-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24target-arm: rename arm_current_pl to arm_current_elGreg Bellows8-47/+50
Renamed the arm_current_pl CPU function to more accurately represent that it returns the ARMv8 EL rather than ARMv7 PL. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1413910544-20150-5-git-send-email-greg.bellows@linaro.org [PMM: fixed a minor merge resolution error in a couple of hunks] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24target-arm: reject switching to monitor modeSergey Fedorov1-0/+2
Reject switching to monitor mode from non-secure state. Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1413910544-20150-4-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24target-arm: add arm_is_secure() functionFabian Aggeler1-0/+47
arm_is_secure() function allows to determine CPU security state if the CPU implements Security Extensions/EL3. arm_is_secure_below_el3() returns true if CPU is in secure state below EL3. Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1413910544-20150-3-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24target-arm: increase arrays of registers R13 & R14Fabian Aggeler2-4/+4
Increasing banked_r13 and banked_r14 to store LR_mon and SP_mon (bank index 7). Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1413910544-20150-2-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0Peter Maydell1-0/+3
The ARM ARM requires that the FPINST and FPINST2 VFP control registers are not accessible to code at EL0. We were already correctly implementing this for reads of these registers; add the missing check for the write code path. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 1412967447-20931-1-git-send-email-peter.maydell@linaro.org
2014-10-24target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any"Peter Maydell1-1/+1
For the CPU type "any" (only used with linux-user) we were reporting the L1Ip field as 0b00, which is reserved. Change this field to 0b10 instead, indicating a VIPT icache as the comment describes. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 1412966807-20844-1-git-send-email-peter.maydell@linaro.org
2014-10-24target-arm: Correct sense of the DCZID DZP bitPeter Maydell2-3/+3
The DZP bit in the DCZID system register should be set if the control bits which prohibit use of the DC ZVA instruction have been set (it stands for Data Zero Prohibited). However we had the sense of the test inverted; fix this so that the bit reads correctly. To avoid this regressing the behaviour of the user-mode emulator, we must set the DZE bit in the SCTLR for that config so that userspace continues to see DZP as zero (it was getting the correct result by accident previously). Reported-by: Christopher Covington <cov@codeaurora.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Christopher Covington <cov@codeaurora.org> Message-id: 1412959792-20708-1-git-send-email-peter.maydell@linaro.org
2014-10-24arm/virt: enable PSCI emulation support for system emulationRob Herring1-44/+38
Now that we have PSCI emulation, enable it for the virt platform. This simplifies the virt machine a bit now that PSCI no longer needs to be a KVM only feature. Signed-off-by: Rob Herring <rob.herring@linaro.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1412865028-17725-8-git-send-email-peter.maydell@linaro.org
2014-10-24target-arm: add emulation of PSCI calls for system emulationRob Herring9-3/+301
Add support for handling PSCI calls in system emulation. Both version 0.1 and 0.2 of the PSCI spec are supported. Platforms can enable support by setting the "psci-conduit" QOM property on the cpus to SMC or HVC emulation and having a PSCI binding in their dtb. Signed-off-by: Rob Herring <rob.herring@linaro.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1412865028-17725-7-git-send-email-peter.maydell@linaro.org [PMM: made system reset/off PSCI functions power down the CPU so we obey the PSCI API requirement never to return from them; rearranged how the code is plumbed into the exception system, so that we split "is this a valid call?" from "do the call"] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24target-arm: Add support for A32 and T32 HVC and SMC insnsPeter Maydell3-11/+104
Add support for HVC and SMC instructions to the A32 and T32 decoder. Using these for real exceptions to EL2 or EL3 is currently not supported (the do_interrupt routine does not handle them) but we require the instruction support to implement PSCI. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1412865028-17725-6-git-send-email-peter.maydell@linaro.org
2014-10-24target-arm: Handle SMC/HVC undef-if-no-ELx in pre_* helpersPeter Maydell2-9/+12
SMC must UNDEF if EL3 is not implemented; similarly HVC UNDEFs if EL2 is not implemented. Move the handling of this from translate-a64.c into the pre_smc and pre_hvc helper functions. This is necessary because use of these instructions for PSCI takes precedence over this UNDEF case, and we can't tell if this is a PSCI call until runtime. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1412865028-17725-5-git-send-email-peter.maydell@linaro.org
2014-10-24target-arm: add missing PSCI constants needed for PSCI emulationArd Biesheuvel1-0/+40
This adds some PSCI function IDs and symbolic return codes that are needed to implement PSCI emulation in TCG mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1412865028-17725-4-git-send-email-peter.maydell@linaro.org
2014-10-24target-arm: do not set do_interrupt handlers for ARM and AArch64 user modesRob Herring4-6/+6
User mode emulation should never get interrupts and thus should not use the system emulation exception handler function. Remove the reference, and '#ifndef USER_MODE_ONLY' the function itself as well, so that we can add system mode only functionality to it. Signed-off-by: Rob Herring <rob.herring@linaro.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1412865028-17725-3-git-send-email-peter.maydell@linaro.org
2014-10-24target-arm: add powered off cpu stateRob Herring3-3/+12
Add tracking of cpu power state in order to support powering off of cores in system emuluation. The initial state is determined by the start-powered-off QOM property. Signed-off-by: Rob Herring <rob.herring@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1412865028-17725-2-git-send-email-peter.maydell@linaro.org
2014-10-24omap_gpmc.c: Remove duplicate assignmentDr. David Alan Gilbert1-2/+0
This looks like an old merge error and should have no effect. (Build tested only) Found by Coccinelle using Julia Lawall's script: https://lkml.org/lkml/2014/8/23/128 Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-id: 1414055855-6688-1-git-send-email-dgilbert@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24disas/libvixl/a64/instructions-a64.h: Remove unused constantsChen Gang1-24/+0
The instructions-a64.h header defines a number of floating point constants whose initializers are function calls. gcc 5 will warn if these constants are not used by the C or C++ file which includes the header, because they imply a runtime cost. Since for the files QEMU uses from libvixl we don't use these constants at all, just remove them. Upstream intend to fix these by shifting to an 'extern const' in the header plus definition in a suitable source file, so we can drop this patch when we sync with the upcoming libvixl 1.7. The related compiling error: CXX disas/arm-a64.o In file included from /upstream/qemu/disas/libvixl/a64/disasm-a64.h:32:0, from disas/arm-a64.cc:20: disas/libvixl/a64/instructions-a64.h:98:13: error: 'vixl::kFP32PositiveInfinity' defined but not used [-Werror=unused-variable] const float kFP32PositiveInfinity = rawbits_to_float(0x7f800000); ^ disas/libvixl/a64/instructions-a64.h:99:13: error: 'vixl::kFP32NegativeInfinity' defined but not used [-Werror=unused-variable] const float kFP32NegativeInfinity = rawbits_to_float(0xff800000); ^ disas/libvixl/a64/instructions-a64.h:100:14: error: 'vixl::kFP64PositiveInfinity' defined but not used [-Werror=unused-variable] const double kFP64PositiveInfinity = ^ disas/libvixl/a64/instructions-a64.h:102:14: error: 'vixl::kFP64NegativeInfinity' defined but not used [-Werror=unused-variable] const double kFP64NegativeInfinity = ^ disas/libvixl/a64/instructions-a64.h:107:21: error: 'vixl::kFP64SignallingNaN' defined but not used [-Werror=unused-variable] static const double kFP64SignallingNaN = ^ disas/libvixl/a64/instructions-a64.h:109:20: error: 'vixl::kFP32SignallingNaN' defined but not used [-Werror=unused-variable] static const float kFP32SignallingNaN = rawbits_to_float(0x7f800001); ^ disas/libvixl/a64/instructions-a64.h:112:21: error: 'vixl::kFP64QuietNaN' defined but not used [-Werror=unused-variable] static const double kFP64QuietNaN = ^ disas/libvixl/a64/instructions-a64.h:114:20: error: 'vixl::kFP32QuietNaN' defined but not used [-Werror=unused-variable] static const float kFP32QuietNaN = rawbits_to_float(0x7fc00001); ^ disas/libvixl/a64/instructions-a64.h:117:21: error: 'vixl::kFP64DefaultNaN' defined but not used [-Werror=unused-variable] static const double kFP64DefaultNaN = ^ disas/libvixl/a64/instructions-a64.h:119:20: error: 'vixl::kFP32DefaultNaN' defined but not used [-Werror=unused-variable] static const float kFP32DefaultNaN = rawbits_to_float(0x7fc00000); ^ cc1plus: all warnings being treated as errors make: *** [disas/arm-a64.o] Error 1 Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> [PMM: Rewrote the commit message a little] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24arm_gic: remove unused parameter.KONRAD Frederic3-4/+4
This removes num_irq parameter from gic_init_irqs_and_distributor as it is not used. Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com> Message-id: 1412859651-15060-1-git-send-email-fred.konrad@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24disas/libvixl: Update to libvixl 1.6Peter Maydell12-332/+715
Update our copy of libvixl to upstream 1.6. There are no changes of any particular interest to QEMU, so this is simply keeping up with current upstream. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1412091418-25744-1-git-send-email-peter.maydell@linaro.org
2014-10-24hw/arm/boot: register cpu reset handlers if using -biosArd Biesheuvel1-5/+12
Move the registering of CPU reset handlers to before the point where we leave the function in the -bios (not -kernel) case, so CPU reset works correctly with -bios as well. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24hw/arm/virt: mark timer in fdt as v8-compatibleClaudio Fontana1-3/+12
check if the first cpu is an armv8 cpu, and if so, put arm,armv8-timer in the compatible string list. Note that due to this check, this patch moves the creation of the timer fdt node to after the cpu creation loop. Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com> Message-id: 1411736960-24206-1-git-send-email-hw.claudio@gmail.com [PMM: updated to list arm,armv8-timer first] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24hmp: Remove "info pcmcia"Markus Armbruster6-82/+0
This command lists PCMCIA sockets and cards. Only a few ARM boards have sockets (akita, borzoi, connex, mainstone, spitz, terrier, tosa, verdex, z2), the only card is the DSCM-1xxxx Hitachi Microdrive (qdev "microdrive"), and it is only inserted during machine init, if ever. So this command doesn't really tell anybody anything new so far. Moreover, pcmcia_socket_unregister() has a use-after-free bug, flagged by Coverity. Has never been used, because there has never been code to eject a PCMCIA card. Not worth fixing & converting to QMP. Remove it. Signed-off-by: Markus Armbruster <armbru@redhat.com> Acked-by: Luiz Capitulino <lcapitulino@redhat.com> Acked-by: Andreas Färber <afaerber@suse.de> Message-id: 1411144812-22958-1-git-send-email-armbru@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into stagingPeter Maydell35-306/+1148
Block patches # gpg: Signature made Thu 23 Oct 2014 18:56:05 BST using RSA key ID C88F2FD6 # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" * remotes/kevin/tags/for-upstream: (32 commits) qemu-img: Print error if check failed block: char devices on FreeBSD are not behind a pager iotests: Add test for qcow2 L1 table update qcow2: Do not overflow when writing an L1 sector iotests: Add test for map commands qemu-io: Respect early image end for map block: Respect underlying file's EOF docs/qcow2: Limit refcount_order to [0, 6] docs/qcow2: Correct refcount_block_entries qcow2: Drop REFCOUNT_SHIFT iotests: Add test for potentially damaging repairs iotests: Fix test outputs qcow2: Clean up after refcount rebuild qcow2: Rebuild refcount structure during check qcow2: Do not perform potentially damaging repairs qcow2: Fix refcount blocks beyond image end qcow2: Reuse refcount table in calculate_refcounts() qcow2: Let inc_refcounts() resize the reftable qcow2: Let inc_refcounts() return -errno qcow2: Split fail code in L1 and L2 checks ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-23Merge remote-tracking branch 'mreitz/block' into queue-blockKevin Wolf2-12/+35
* mreitz/block: qemu-img: Print error if check failed block: char devices on FreeBSD are not behind a pager
2014-10-23qemu-img: Print error if check failedMax Reitz1-7/+14
Currently, if bdrv_check() fails either by returning -errno or having check_errors set, qemu-img check just exits with 1 after having told the user that there were no errors on the image. This is bad. Instead of printing the check result if there were internal errors which were so bad that bdrv_check() could not even complete with 0 as a return value, qemu-img check should inform the user about the error. Signed-off-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com>
2014-10-23Merge remote-tracking branch 'remotes/qmp-unstable/tags/for-upstream' into ↵Peter Maydell6-218/+216
staging QMP patches # gpg: Signature made Thu 23 Oct 2014 16:05:52 BST using RSA key ID E24ED5A7 # gpg: Good signature from "Luiz Capitulino <lcapitulino@gmail.com>" * remotes/qmp-unstable/tags/for-upstream: monitor: delete device_del_bus_completion monitor: add del completion for peripheral device qdev: add qdev_build_hotpluggable_device_list helper MAINTAINERS: add entry for qobject files dump: Turn some functions to void to make code cleaner dump: Propagate errors into qmp_dump_guest_memory() virtio-balloon: Tweak recent fix for integer overflow Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-23block: char devices on FreeBSD are not behind a pagerRoger Pau Monne1-5/+21
Introduce a new flag to mark devices that require requests to be aligned and replace the usage of BDRV_O_NOCACHE and O_DIRECT with this flag when appropriate. If a character device is used as a backend on a FreeBSD host set this flag unconditionally. Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Cc: Kevin Wolf <kwolf@redhat.com> Cc: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Max Reitz <mreitz@redhat.com>
2014-10-23iotests: Add test for qcow2 L1 table updateMax Reitz3-0/+72
Updating the L1 table should not result in random data being written. This adds a test for that. Signed-off-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2014-10-23qcow2: Do not overflow when writing an L1 sectorMax Reitz1-2/+4
While writing an L1 table sector, qcow2_write_l1_entry() copies the respective range from s->l1_table to the local "buf" array. The size of s->l1_table does not have to be a multiple of L1_ENTRIES_PER_SECTOR; thus, limit the index which is used for copying all entries to the L1 size. Cc: qemu-stable@nongnu.org Signed-off-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Peter Lieven <pl@kamp.de> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2014-10-23iotests: Add test for map commandsMax Reitz3-0/+75
Add a test for qemu-img map and qemu-io -c map on truncated files. Signed-off-by: Max Reitz <mreitz@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2014-10-23qemu-io: Respect early image end for mapMax Reitz1-1/+4
bdrv_is_allocated() may report zero clusters which most probably means the image (file) is shorter than expected. Respect this case in order to avoid an infinite loop. Signed-off-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Benoît Canet <benoit.canet@nodalink.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2014-10-23block: Respect underlying file's EOFMax Reitz1-2/+13
When falling through to the underlying file in bdrv_co_get_block_status(), if it returns that the query offset is beyond the file end (by setting *pnum to 0), return the range to be zero and do not let the number of sectors for which information could be obtained be overwritten. Signed-off-by: Max Reitz <mreitz@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2014-10-23docs/qcow2: Limit refcount_order to [0, 6]Max Reitz1-0/+1
Specify the upper limit of refcount_order to be 6 (that is, refcount_bits = 64). Any larger value does not make much sense when all offsets, sizes, cluster counts etc. "only" have a width of 64 bit as well, and very large values would be very difficult to support. Therefore, just cap it at the largest reasonable value. Suggested-by: Eric Blake <eblake@redhat.com> Signed-off-by: Max Reitz <mreitz@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2014-10-23docs/qcow2: Correct refcount_block_entriesMax Reitz1-1/+1
A refblock entry may have a different size than 16 bits, it may even be smaller than a byte. Correct the refcount_block_entries calculation accordingly. Signed-off-by: Max Reitz <mreitz@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2014-10-23qcow2: Drop REFCOUNT_SHIFTMax Reitz3-21/+15
With BDRVQcowState.refcount_block_bits, we don't need REFCOUNT_SHIFT anymore. Signed-off-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2014-10-23iotests: Add test for potentially damaging repairsMax Reitz3-0/+252
There are certain cases where repairing a qcow2 image might actually damage it further (or rather, where repairing it has in fact damaged it further with the old qcow2 check implementation). This should not happen, so add a test for these cases. Furthermore, the repair function now repairs refblocks beyond the image end by resizing the image accordingly. Add several tests for this as well. Signed-off-by: Max Reitz <mreitz@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2014-10-23iotests: Fix test outputsMax Reitz3-10/+28
039, 060 and 061 all create images with referenced clusters having a refcount of 0. Because previous commits changed handling of such errors, these tests now have a different output. Fix it. Furthermore, 060 created a refblock with a refcount greater than one which now results in having to rebuild the refcount structure as well. Signed-off-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2014-10-23qcow2: Clean up after refcount rebuildMax Reitz1-0/+45
Because the old refcount structure will be leaked after having rebuilt it, we need to recalculate the refcounts and run a leak-fixing operation afterwards (if leaks should be fixed at all). Signed-off-by: Max Reitz <mreitz@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2014-10-23qcow2: Rebuild refcount structure during checkMax Reitz1-6/+305
The previous commit introduced the "rebuild" variable to qcow2's implementation of the image consistency check. Now make use of this by adding a function which creates a completely new refcount structure based solely on the in-memory information gathered before. The old refcount structure will be leaked, however. This leak will be dealt with in a follow-up commit. Signed-off-by: Max Reitz <mreitz@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2014-10-23qcow2: Do not perform potentially damaging repairsMax Reitz1-161/+27
If a referenced cluster has a refcount of 0, increasing its refcount may result in clusters being allocated for the refcount structures. This may overwrite the referenced cluster, therefore we cannot simply increase the refcount then. In such cases, we can either try to replicate all the refcount operations solely for the check operation, basing the allocations on the in-memory refcount table; or we can simply rebuild the whole refcount structure based on the in-memory refcount table. Since the latter will be much easier, do that. To prepare for this, introduce a "rebuild" boolean which should be set to true whenever a fix is rather dangerous or too complicated using the current refcount structures. Another example for this is refcount blocks being referenced more than once. Signed-off-by: Max Reitz <mreitz@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2014-10-23qcow2: Fix refcount blocks beyond image endMax Reitz1-4/+63
If the qcow2 check function detects a refcount block located beyond the image end, grow the image appropriately. This cannot break anything and is the logical fix for such a case. Signed-off-by: Max Reitz <mreitz@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2014-10-23qcow2: Reuse refcount table in calculate_refcounts()Max Reitz1-5/+7
We will later call calculate_refcounts multiple times, so reuse the refcount table if possible. Signed-off-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Benoît Canet <benoit.canet@nodalink.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2014-10-23qcow2: Let inc_refcounts() resize the reftableMax Reitz1-22/+35
Now that the refcount table can be passed around by reference, do that for inc_refcounts() (and subsequently check_refcounts_l1() and check_refcounts_l2()) and use it for resizing it when a cluster after the image end is encountered. Signed-off-by: Max Reitz <mreitz@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2014-10-23qcow2: Let inc_refcounts() return -errnoMax Reitz1-31/+60
As of a future patch, inc_refcounts() will have to throw errors which are generally signaled by returning -errno. Therefore, let it return an integer which is either 0 for success or -errno and handle the -errno case in all callers. Signed-off-by: Max Reitz <mreitz@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2014-10-23qcow2: Split fail code in L1 and L2 checksMax Reitz1-9/+14
Instead of printing out an error message, incrementing check_errors and returning a fixed -errno, just do cleanups and return -ret, with ret set by the code which threw the exception (jumped to the fail label). Also, increment check_errors on error in check_refcounts_l2(). Signed-off-by: Max Reitz <mreitz@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2014-10-23qcow2: Use int64_t for in-memory reftable sizeMax Reitz1-3/+3
Use int64_t for the entry count of the in-memory refcount table throughout the check functions. Signed-off-by: Max Reitz <mreitz@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
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