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2014-12-16disas/mips: disable unused mips16_to_32_reg_map[]Leon Alrae1-1/+2
2014-12-16disas/mips: remove unused mips_msa_control_names_numeric[32]Leon Alrae1-7/+0
2014-12-16target-mips: convert single case switch into if statementLeon Alrae1-3/+1
2014-12-16target-mips: Fix DisasContext's ulri member initializationMaciej W. Rozycki1-1/+1
2014-12-16target-mips: Use local float status pointer across MSA macrosMaciej W. Rozycki1-35/+34
2014-12-16target-mips: Add missing calls to synchronise SoftFloat statusMaciej W. Rozycki4-17/+17
2014-12-16linux-user: Use the 5KEf processor for 64-bit emulationMaciej W. Rozycki1-1/+1
2014-12-16target-mips: Also apply the CP0.Status mask to MTTC0Maciej W. Rozycki1-1/+2
2014-12-16target-mips: gdbstub: Clean up FPU register handlingMaciej W. Rozycki1-19/+19
2014-12-16target-mips: Correct 32-bit address space wrappingMaciej W. Rozycki2-8/+19
2014-12-16target-mips: Tighten ISA level checksMaciej W. Rozycki3-15/+114
2014-12-16target-mips: Fix CP0.Config3.ISAOnExc write accessesMaciej W. Rozycki3-2/+15
2014-12-16target-mips: Output CP0.Config2-5 in the register dumpMaciej W. Rozycki1-0/+4
2014-12-16target-mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEPMaciej W. Rozycki1-3/+3
2014-12-16target-mips: Correct the writes to Status and Cause registers via gdbstubMaciej W. Rozycki3-86/+102
2014-12-16target-mips: Correct the handling of writes to CP0.Status for MIPSr6Maciej W. Rozycki1-2/+4
2014-12-16target-mips: Correct MIPS16/microMIPS branch size calculationMaciej W. Rozycki2-2/+3
2014-12-16target-mips: Restore the order of helpersMaciej W. Rozycki1-159/+160
2014-12-16target-mips: Remove unused `FLOAT_OP' macroMaciej W. Rozycki1-2/+0
2014-12-16target-mips: Make `helper_float_cvtw_s' consistent with the remaining helpersMaciej W. Rozycki1-1/+1
2014-12-16target-mips: Fix formatting in `decode_opc'Maciej W. Rozycki1-5/+8
2014-12-16target-mips: Fix formatting in `mips_defs'Maciej W. Rozycki1-19/+21
2014-12-16target-mips: Fix formatting in `decode_extended_mips16_opc'Maciej W. Rozycki1-1/+1
2014-12-16target-mips: Enable vectored interrupt support for the 74Kf CPUMaciej W. Rozycki1-1/+1
2014-12-16target-mips: Add M14K and M14Kc MIPS32r2 microMIPS processorsMaciej W. Rozycki1-0/+41
2014-12-16target-mips: Make CP0.Config4 and CP0.Config5 registers signedMaciej W. Rozycki1-4/+4
2014-12-16target-mips: Add 5KEc and 5KEf MIPS64r2 processorsMaciej W. Rozycki1-0/+45
2014-12-16target-mips: Make CP1.FIR read-only here tooMaciej W. Rozycki1-1/+1
2014-12-16target-mips: Correct the handling of register #72 on writesMaciej W. Rozycki1-1/+1
2014-12-15Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell44-263/+604
2014-12-15sdhci: Support SDHCI devices on PCIKevin O'Connor3-1/+54
2014-12-15sdhci: Define SDHCI PCI idsKevin O'Connor3-0/+4
2014-12-15sdhci: Add "sysbus" to sdhci QOM types and methodsKevin O'Connor2-18/+27
2014-12-15sdhci: Remove class "virtual" methodsKevin O'Connor2-106/+40
2014-12-15sdhci: Set a default frequency clockKevin O'Connor1-2/+2
2014-12-15serial: only resample THR interrupt on rising edge of IER.THRIPaolo Bonzini1-9/+16
2014-12-15serial: update LSR on enabling/disabling FIFOsPaolo Bonzini1-0/+3
2014-12-15serial: clean up THRE/TEMT handlingPaolo Bonzini1-14/+12
2014-12-15serial: reset thri_pending on IER writes with THRI=0Paolo Bonzini1-2/+16
2014-12-15linuxboot: fix loading old kernelsPaolo Bonzini2-10/+27
2014-12-15kvm/apic: fix 2.2->2.1 migrationPaolo Bonzini3-3/+13
2014-12-15target-i386: add Ivy Bridge CPU modelPaolo Bonzini1-0/+32
2014-12-15target-i386: add f16c and rdrand to Haswell and BroadwellPaolo Bonzini3-2/+10
2014-12-15target-i386: add VME to all CPUsPaolo Bonzini3-15/+43
2014-12-15pc: add 2.3 machine typesPaolo Bonzini2-7/+48
2014-12-15i386: do not cross the pages boundaries in replay modePavel Dovgalyuk2-0/+17
2014-12-15cpus: make icount warp behave well with respect to stop/contPavel Dovgalyuk2-12/+12
2014-12-15timer: introduce new QEMU_CLOCK_VIRTUAL_RT clockPavel Dovgalyuk2-0/+9
2014-12-15cpu-exec: invalidate nocache translation if they are interruptedPavel Dovgalyuk3-1/+8
2014-12-15icount: introduce cpu_get_icount_rawPavel Dovgalyuk2-3/+11
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