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2012-09-22target-xtensa: implement FP0 conversionsMax Filippov3-0/+89
These are FP to integer and integer to FP conversion opcodes. See ISA, 4.3.10 for more details. Note that ISA description for utrunc.s is currently incorrect and will be fixed in future revisions. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-09-22target-xtensa: implement FP0 arithmeticMax Filippov3-1/+104
These are FP arithmetic opcodes. See ISA, 4.3.10 for more details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-09-22target-xtensa: implement LSCX and LSCI groupsMax Filippov1-4/+54
These are load/store instructions for FP registers with immediate or register index and optional base post-update. See ISA, 4.3.10 for more details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-09-22target-xtensa: add FP registersMax Filippov5-7/+71
There are 16 32-bit FP registers (f0 - f15), control and status user registers (fcr, fsr). See ISA, 4.3.10 for more details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-09-22target-xtensa: specialize softfloat NaN rulesMax Filippov1-2/+3
NaN propagation rule: leftmost NaN in the expression gets propagated to the result. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-09-22target-xtensa: handle boolean option in overlaysMax Filippov1-0/+1
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-09-22softfloat: add NO_SIGNALING_NANSMax Filippov2-0/+72
Architectures that don't have signaling NaNs can define NO_SIGNALING_NANS, it will make float*_is_quiet_nan return 1 for any NaN and float*_is_signaling_nan always return 0. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-09-22softfloat: make float_muladd_negate_* flags independentMax Filippov1-1/+1
Flags passed into float{32,64}_muladd are treated as bits; assign independent bits to float_muladd_negate_* to allow precise control over what gets negated in float{32,64}_muladd. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-09-22Revert "tcg/mips"Aurelien Jarno1-2/+2
This reverts commit ad49d1f75115663731bfe06dec61eed6775526ad. This commit was not supposed to be pushed. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/ppc32: Implement movcond32malc2-1/+76
Thanks to Richard Henderson Signed-off-by: malc <av1474@comtv.ru>
2012-09-22tcg/mipsAurelien Jarno1-2/+2
2012-09-22tcg: Remove tcg_target_get_call_iarg_regs_countStefan Weil11-61/+1
The TCG targets no longer need individual implementations. Since commit 6a18ae2d2947532d5c26439548afa0481c4529f9, 'flags' is no longer used in tcg_target_get_call_iarg_regs_count. The remaining tcg_target_get_call_iarg_regs_count is trivial and only called once. Therefore the patch eliminates it completely. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/i386: Remove unused registers from tcg_target_call_iarg_regsStefan Weil1-8/+2
32 bit x86 hosts don't need registers for helper function arguments because they use the default stack based calling convention. Removing the registers allows simpler code for function tcg_target_get_call_iarg_regs_count. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/i386: Add shortcuts for registers used in L constraintStefan Weil1-48/+48
While 64 bit hosts use the first three registers which are also used as function input parameters, 32 bit hosts use TCG_REG_EAX and TCG_REG_EDX which are not used in parameter passing. After defining new register macros for the registers used in L constraint, the patch replaces most occurrences of tcg_target_call_iarg_regs[0], tcg_target_call_iarg_regs[1] and tcg_target_call_iarg_regs[2] by those new macros. tcg_target_call_iarg_regs remains unchanged when it is used for input arguments (only with 64 bit hosts) before tcg_out_calli. A comment related to those registers was fixed, too. Signed-off-by: Stefan Weil <sw@weilnetz.de> [aurel32: build fix on i386, small optimization for i386 in the prologue] Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22w64: Fix TCG helper functions with 5 argumentsStefan Weil2-1/+5
TCG uses 6 registers for function arguments on 64 bit Linux hosts, but only 4 registers on W64 hosts. Commit 2999a0b20074a7e4a58f56572bb1436749368f59 increased the number of arguments for some important helper functions from 4 to 5 which triggered a bug for W64 hosts: QEMU aborts when executing helper_lcall_real in the guest's BIOS because function tcg_target_get_call_iarg_regs_count always returned 6. As W64 has only 4 registers for arguments, the 5th argument must be passed on the stack using a correct stack offset. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/README: document tcg_gen_goto_tb restrictionsMax Filippov1-1/+2
See http://lists.nongnu.org/archive/html/qemu-devel/2012-09/msg03196.html for the whole story. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg-hppa: Implement movcondRichard Henderson2-1/+22
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/optimize: add constant folding for depositAurelien Jarno1-0/+20
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg: remove #ifdef #endif around TCGOpcode testsAurelien Jarno1-12/+1
Commit 25c4d9cc changed all TCGOpcode enums to be available, so we don't need to #ifdef #endif the one that are available only on some targets. This makes the code easier to read. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/optimize: prefer the "op a, a, b" form for commutative opsAurelien Jarno1-1/+4
The "op a, a, b" form is better handled on non-RISC host than the "op a, b, a" form, so swap the arguments to this form when possible, and when b is not a constant. This reduces the number of generated instructions by a tiny bit. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/optimize: further optimize brcond/movcond/setcondAurelien Jarno1-51/+76
When both argument of brcond/movcond/setcond are the same or when one of the two values is a constant equal to zero, it's possible to do further optimizations. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/optimize: optimize "op r, a, a => movi r, 0"Aurelien Jarno1-0/+16
Now that it's possible to detect copies, we can optimize the case the "op r, a, a => movi r, 0". This helps in the computation of overflow flags when one of the two args is 0. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/optimize: optimize "op r, a, a => mov r, a"Aurelien Jarno1-1/+1
Now that we can easily detect all copies, we can optimize the "op r, a, a => mov r, a" case a bit more. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/optimize: do copy propagation for all operationsAurelien Jarno1-2/+9
It is possible to due copy propagation for all operations, even the one that have side effects or clobber arguments (it only concerns input arguments). That said, the call operation should be handled differently due to the variable number of arguments. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/optimize: rework copy progagationAurelien Jarno1-75/+92
The copy propagation pass tries to keep track what is a copy of what and what has copy of what, and in addition it keep a circular list of of all the copies. Unfortunately this doesn't fully work: a mov from a temp which has a state "COPY" changed it into a state "HAS_COPY". Later when this temp is used again, it is considered has not having copy and thus no propagation is done. This patch fixes that by removing the hiearchy between copies, and thus only keeping a "COPY" state both meaning "is a copy" and "has a copy". The decision of which copy to use is deferred to the actual temp replacement. At this stage there is not one best choice to do, but only better choices than others. For doing the best choice the operation would have to be parsed in reversed to know if a temp is going to be used later or not. That what is done by the liveness analysis. At this stage it is known that globals will be always live, that local temps will be dead at the end of the translation block, and that the temps will be dead at the end of the basic block. This means that this stage should try to replace temps by local temps or globals and local temps by globals. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/optimize: check types in copy propagationAurelien Jarno1-10/+8
The copy propagation doesn't check the types of the temps during copy propagation. However TCG is using the mov_i32 for the i64 to i32 conversion and thus the two are not equivalent. With this patch tcg_opt_gen_mov() doesn't consider two temps of different type as copies anymore. So far it seems the optimization was not aggressive enough to trigger this bug, but it will be triggered later in this series once the copy propagation is improved. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/optimize: remove TCG_TEMP_ANYAurelien Jarno1-6/+5
TCG_TEMP_ANY has no different meaning than TCG_TEMP_UNDEF, so use the later instead. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/mips: implement movcond op on MIPS32R2Aurelien Jarno2-0/+77
movcond operation can be implemented on MIPS32 Release 2 using the MOVN, MOVZ, SLT and SLTU instructions. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/mips: implement deposit op on MIPS32R2Aurelien Jarno2-1/+10
deposit operations can be optimized on MIPS32 Release 2 using the INS instruction. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/mips: implement rotl/rotr ops on MIPS32R2Aurelien Jarno2-1/+22
rotr operations can be optimized on MIPS32 Release 2 using the ROTR and ROTRV instructions. Also implemented rotl operations by subtracting the shift from 32. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/mips: optimize bswap{16,16s,32} on MIPS32R2Aurelien Jarno2-7/+38
bswap operations can be optimized on MIPS32 Release 2 using the ROTR, WSBH and SEH instructions. We can't use the non-R2 code to implement the ops due to registers constraints, so don't define the corresponding TCG_TARGET_HAS_bswap* values. Also bswap16* operations are supposed to be called with the 16 high bits zeroed. This is the case everywhere (including for TCG by definition) except when called from the store helper. Remove the AND instructions from bswap16* and move it there. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/mips: optimize brcond arg, 0Aurelien Jarno1-8/+30
MIPS has some conditional branch instructions when comparing with zero. Use them. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/mips: use stack for TCG tempsAurelien Jarno1-4/+6
Use stack instead of temp_buf array in CPUState for TCG temps. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/mips: don't use global pointerAurelien Jarno1-1/+1
Don't use the global pointer in TCG, in case helpers try access global variables. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/mips: use TCGArg or TCGReg instead of intAurelien Jarno1-28/+35
Instead of int, use the correct TCGArg and TCGReg type: TCGReg when representing a TCG target register, TCGArg when representing the latter or a constant. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg/mips: kill warnings in user modeAurelien Jarno1-41/+43
Recent versions of GCC emit warnings when compiling user mode targets. Kill them by reordering a bit the #ifdef. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-22tcg-mips: fix wrong usage of 'Z' constraintAurelien Jarno1-8/+8
The 'Z' constraint has been introduced to map the zero register. However when the op also accept a constant, there is no point to accept the zero register in addition. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-21tcg-sparc: Preserve branch destinations during retranslationRichard Henderson1-8/+11
Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-21tcg-sparc: Fix and enable direct TB chaining.Richard Henderson2-6/+24
Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-21tcg-sparc: Add %g/%o registers to alloc_orderRichard Henderson1-0/+13
Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-21tcg-sparc: Use defines for temporaries.Richard Henderson1-56/+59
And change from %i4/%i5 to %g1/%o7 to remove a v8plus fixme. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-21tcg-sparc: Mask shift immediates to avoid illegal insns.Richard Henderson1-6/+12
The xtensa-test image generates a sra_i32 with count 0x40. Whether this is accident of tcg constant propagation or originating directly from the instruction stream is immaterial. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-21tcg-sparc: Clean up cruft stemming from attempts to use global registers.Richard Henderson3-59/+26
Don't use -ffixed-gN. Don't link statically. Don't save/restore AREG0 around calls. Don't allocate space on the stack for AREG0 save. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-21tcg-sparc: Change AREG0 in generated code to %i0.Richard Henderson2-8/+3
We can now move the TCG variable from %g[56] to a call-preserved windowed register. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-21tcg-sparc: Support GUEST_BASE.Richard Henderson3-3/+27
Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-21tcg-sparc: Fix qemu_ld/st to handle 32-bit host.Richard Henderson1-429/+348
At the same time, split out the tlb load logic to a new function. Fixes the cases of two data registers and two address registers. Fixes the signature of, and adds missing, qemu_ld/st opcodes. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-21tcg-sparc: Assume v9 cpu always, i.e. force v8plus in 32-bit mode.Richard Henderson7-63/+23
Current code doesn't actually work in 32-bit mode at all. Since no one really noticed, drop the complication of v7 and v8 cpus. Eliminate the --sparc_cpu configure option and standardize macro testing on TCG_TARGET_REG_BITS / HOST_LONG_BITS Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-21tcg-sparc: Don't MAP_FIXED on top of the programRichard Henderson1-4/+2
The address we pick in sparc64.ld is also 0x60000000, so doing a fixed map on top of that is guaranteed to blow up. Choosing 0x40000000 is exactly right for the max of code_gen_buffer_size set below. No need to ever use MAP_FIXED. While getting our desired address helps optimize the generated code, we won't fail if we don't get it. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-21tcg-sparc: Fix ADDX opcode.Richard Henderson1-1/+1
Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-09-21tcg-sparc: Hack in qemu_ld/st64 for 32-bit.Richard Henderson1-0/+3
Not actually implemented, but at least we avoid the tcg assert at startup. Signed-off-by: Richard Henderson <rth@twiddle.net>
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