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2011-10-19target-arm: Implement VFPv4 fused multiply-accumulate insnsPeter Maydell4-0/+90
Implement the fused multiply-accumulate instructions (VFMA, VFMS, VFNMA, VFNMS) which are new in VFPv4. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-10-19softfloat: Implement fused multiply-addPeter Maydell3-0/+619
Implement fused multiply-add as a softfloat primitive. This implements "a+b*c" as a single step without any intermediate rounding; it is specified in IEEE 754-2008 and implemented in a number of CPUs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-10-19target-arm: Add ARM UDIV/SDIV supportPeter Maydell3-1/+24
Add support for UDIV and SDIV in ARM mode. This is a new optional feature for A profile cores (Thumb mode has had UDIV and SDIV for M profile cores for some time). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-10-19target-arm: Rename ARM_FEATURE_DIV to _THUMB_DIVPeter Maydell3-4/+5
Rename the ARM_FEATURE_DIV feature bit to _THUMB_DIV, to make room for a new feature switch enabling DIV in the ARM encoding. (Cores may implement either (a) no divide insns (b) divide insns in Thumb encodings only (c) divide insns in both ARM and Thumb encodings.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-10-19target-arm: v6 media multiply space: UNDEF on unassigned encodingsPeter Maydell1-4/+20
Clean up the decoding of the v6 media multiply space so that we UNDEF on unassigned encodings rather than randomly interpreting them as some instruction in this space. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-10-19rsqrte_f32: No need to copy sign bit.Christophe LYON1-2/+1
Indeed, the result is known to be always positive. Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-10-16i8259: Move to hw libraryJan Kiszka12-4/+15
No target-specific bits remaining, let's move it over. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16monitor: Restrict pic/irq_info to supporting targetsJan Kiszka14-77/+33
This allows to drop various stubs and move the i8359 into hwlib. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16i8259: Fix coding styleJan Kiszka1-20/+34
No functional changes. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16i8259: Convert to qdevJan Kiszka1-57/+100
This key cleanup step requires to move the IRQ debugging bit from i8259_set_irq directly to the per-PIC pic_set_irq, to pass the PIC parameters (I/O base, ELCR address and mask, master/slave mode) as qdev properties, and to interconnect the PICs with their environment via GPIO pins. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16qdev: Add HEX8 propertyJan Kiszka2-0/+32
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16i8259: Eliminate PicState2Jan Kiszka2-35/+34
Introduce a reference to the slave PIC for the few cases we need to access it without a proper pointer at hand and drop PicState2. We could even live without slave_pic if we had a better way of modeling the cascade bus the PICs are attached to (in addition to the ISA bus). Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16i8259: Replace PicState::pics_state with master flagJan Kiszka1-9/+9
This reflects how real PICs indentify their role (in non-buffered mode): Pass the state of the /SP input on pic_init and use it instead of pics_state to differentiate between master and slave mode. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16i8259: PREP: Replace pic_intack_read with pic_read_irqJan Kiszka3-41/+1
There is nothing in the i8259 spec that justifies the special pic_intack_read. At least the Linux PREP kernels configure the PICs properly so that pic_read_irq returns identical values, and setting read_reg_select in PIC0 cannot be derived from any special i8259 mode. So switch ppc_prep to pic_read_irq and drop the now unused PIC code. CC: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16i8259: Clean up pic_ioport_readJan Kiszka1-2/+1
Drop redundant local address variable. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16i8259: Fix poll commandJan Kiszka1-1/+7
This was probably never used so far: According to the spec, polling means ack'ing the pending IRQ and setting its corresponding bit in isr. Moreover, we have to signal a pending IRQ via bit 7 of the returned value, and we must not return a spurious IRQ if none is pending. This implements the poll command without the help of pic_poll_read which is left untouched as pic_intack_read is still using it. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16i8259: Switch to per-PIC IRQ updateJan Kiszka1-40/+21
This converts pic_update_irq to work against a single PIC instead of the complete cascade. Along this change, the required update after pic_set_irq1 is now moved into that function. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16i8259: Clear ELCR on resetJan Kiszka1-5/+10
The ELCR is actually part of the chipset but we model it here for simplicity reasons. The PIIX3 clears the ELCR on reset, which was once broken by 4dbe19e181. Fix this by splitting up pic_init_reset from pic_reset and clearing the register in the latter. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16i8259: Update IRQ state after resetJan Kiszka1-2/+1
MIPS and PPC users of the i8259 output signal expect us to report state updates also after reset. As no consumer (including the master PIC) can misinterpret the deassert as an activation event, it is safe to simply update the IRQ state after reset. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16i8259: Reorder intack in pic_read_irqJan Kiszka1-4/+6
As we want to move the IRQ update to pic_intack, ordering matters: the slave ack must be executed before the master ack to avoid missing further pending slave IRQs. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16i8259: Do not update IRQ output after spurious pic_poll_readJan Kiszka1-1/+0
If pic_poll_read finds no pending IRQ and return a spurious one instead, no PIC state is changed, thus we do not need to call pic_update_irq. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16i8239: Introduce per-PIC output interruptJan Kiszka1-9/+12
As a first step towards more generic master-slave support, remove parent_irq in favor of a per-PIC output interrupt line. The slave's line is attached to IRQ2 of the master, but it remains unused for now. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16i8259: Move pic_set_irq1 after pic_update_irqJan Kiszka1-26/+29
We are about to call the latter from the former. No functional changes. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16i8259: Drop obsolete prototypesJan Kiszka1-2/+0
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16i8259: Remove premature inline function attributesJan Kiszka1-3/+3
The compiler is smarter in choosing the right optimization. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16pc: Fix and clean up PIC-to-APIC IRQ pathJan Kiszka4-12/+12
The master PIC is connected to the LINTIN0 of the APICs. As the APIC currently does not track the state of that line, we have to ask the PIC to reinject its IRQ after the CPU picked up an event from the APIC. This introduces pic_get_output to read the master PIC IRQ line state without changing it. The APIC uses this function to decide if a PIC IRQ should be reinjected on apic_update_irq. This reflects better how the real hardware works. The patch fixes some failures of the kvm unit tests apic and eventinj by allowing to enable the proper CPU IRQ deassertion when the guest masks some pending IRQs at PIC level. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16pc: Convert GSIState::i8259_irq into arrayJan Kiszka2-2/+4
Will be required when we no longer let i8259_init allocate the PIC IRQs but convert that chips to qdev. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16pc: Generalize ISA IRQs to GSIsJan Kiszka5-31/+42
The ISA bus IRQ range is 0..15. What isa_irq_handler and IsaIrqState are actually dealing with are the Global System Interrupts. Refactor the code to clarify this. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16pc: Drop useless test from isa_irq_handlerJan Kiszka1-3/+2
IsaIrqState::ioapic is always non-NULL. Probably, the concrete qemu_irq was supposed to be tested, but that's already done by qemu_set_irq. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16target-xtensa: add Avnet LX60/LX110/LX200 boardsMax Filippov4-0/+240
These boards carry similar hardware: SDRAM (48M for LX110, 64M for LX60, 96M for LX200), 16 Mbyte FLASH, FPGA, 10/100 Mbps Ethernet PHY and 16550 UART. FPGA may be loaded with almost any Tensilica processor. It is also used to implement Ethernet MAC, e.g. OpenCores 10/100 Mbps Ethernet MAC and LED/DIP switches access. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16hw: add OpenCores 10/100 Mbps Ethernet controllerMax Filippov3-0/+743
This is OpenCores Ethernet MAC + subset of National Semiconductors DP83838C PHY. OpenCores Ethernet MAC project: http://opencores.org/project,ethmac Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16target-xtensa: rename dc232b board to simMax Filippov3-15/+15
This is to get aligned with the linux name for this machine. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16target-xtensa: add fsf coreMax Filippov3-0/+384
This is FSF big endian core implemented through linux overlay. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16target-xtensa: add dc232b coreMax Filippov4-0/+713
This is Diamond 232L Standard Core Rev.B (LE), implemented through linux/gdb overlay. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16target-xtensa: extract core configuration from overlayMax Filippov3-13/+554
Introduce overlay_tool.h that defines core configuration blocks from data available in the linux architecture variant overlay. Overlay data is automatically generated in the core configuration process by Tensilica tools and can be directly converted to qemu xtensa core description by overlay_tool.h Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16target-xtensa: implement external interrupt mappingMax Filippov2-0/+15
Xtensa cores may have different mapping of external interrupt pins to internal IRQ numers. Implement API to acquire core IRQ by its external interrupt number. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16target-xtensa: remove hand-written xtensa cores implementationsMax Filippov5-968/+2
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16target-xtensa: increase xtensa options accuracyMax Filippov2-8/+12
- add separate options for each operation in the MISC_OP; - add an option for MULSH/MULUH; - put S32C1I under conditional store option. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-15target-xtensa: update qemu-doc.texiMax Filippov2-7/+88
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-15target-xtensa: add MAC16 unit testsMax Filippov2-0/+244
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-15target-xtensa: implement MAC16 optionMax Filippov2-1/+137
See ISA, 4.3.7 for the details. - add ACC and MR special registers; - implement MAC16 and all inner MAC* opcode groups. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-15target-xtensa: fix guest hang on masked CCOMPARE interruptMax Filippov4-16/+93
QEMU timer is used to post CCOMPARE interrupt when the core is halted. If that CCOMPARE interrupt is masked off then the timer must be rearmed in the callback, otherwise it will be rearmed next time the core goes to halt by the waiti instruction. Add test case into timer testsuite. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-15Drop obsolete nographic timerJan Kiszka1-13/+0
We flush coalesced MMIO in the device models now, and VNC - for which this was once introduced - is also fine without it as it has its own refresh timer. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-15Move graphic-related coalesced MMIO flushes to affected device modelsJan Kiszka3-2/+8
This is conceptually cleaner and will allow us to drop the nographic timer. Moreover, it will be mandatory to fully exploit future per-device coalesced MMIO rings. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-14Merge remote-tracking branch 'kwolf/for-anthony' into stagingAnthony Liguori12-633/+283
2011-10-14Merge remote-tracking branch 'stefanha/trivial-patches' into stagingAnthony Liguori7-32/+10
2011-10-14Merge remote-tracking branch 'kraxel/usb.28' into stagingAnthony Liguori9-84/+180
2011-10-14Merge remote-tracking branch 'qemu-kvm-tmp/memory/batch' into stagingAnthony Liguori37-394/+535
2011-10-14block: drop bdrv_has_async_rw()Stefan Hajnoczi1-6/+0
Commit cd74d83345e0e3b708330ab8c4cd9111bb82cda6 ("block: switch bdrv_read()/bdrv_write() to coroutines") removed the bdrv_has_async_rw() callers. This patch removes bdrv_has_async_rw() since it is no longer used. Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2011-10-14block: drop .bdrv_read()/.bdrv_write() emulationStefan Hajnoczi1-72/+3
There is no need to emulate .bdrv_read()/.bdrv_write() since these interfaces are only called if aio and coroutine interfaces are not present. All valid BlockDrivers must implement either sync, aio, or coroutine interfaces. Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
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