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2011-04-12cpu-common: Modify cpu_physical_memory_read and cpu_physical_memory_writeStefan Weil1-3/+3
A lot of calls don't operate on bytes but on words or on structured data. So instead of a pointer to uint8_t, a void pointer is the better choice. This allows removing many type casts. (Some very early implementations of memcpy used char pointers which were replaced by void pointers for the same reason). Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-15Add qemu_ram_remapHuang Ying1-0/+1
qemu_ram_remap() unmaps the specified RAM pages, then re-maps these pages again. This is used by KVM HWPoison support to clear HWPoisoned page tables across guest rebooting, so that a new page may be allocated later to recover the memory error. [ Jan: style fixlets, WIN32 fix ] Signed-off-by: Huang Ying <ying.huang@intel.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2011-02-14Introduce log_start/log_stop in CPUPhysMemoryClientAnthony PERARD1-0/+4
In order to use log_start/log_stop with Xen as well in the vga code, this two operations have been put in CPUPhysMemoryClient. The two new functions cpu_physical_log_start,cpu_physical_log_stop are used in hw/vga.c and replace the kvm_log_start/stop. With this, vga does no longer depends on kvm header. [ Jan: rebasing and style fixlets ] Signed-off-by: Anthony PERARD <anthony.perard@citrix.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2010-12-11exec: introduce endianness swapped mmioAlexander Graf1-1/+7
The way we're currently modeling mmio is too simplified. We assume that every device has the same endianness as the target CPU. In reality, most devices are little endian (all PCI and ISA ones I'm aware of). Some are big endian (special system devices) and a very little fraction is target native endian (fw_cfg). So instead of assuming every device to be native endianness, let's move to a model where the device tells us which endianness it's in. That way we can compile the devices only once and get rid of all the ugly swap will be done by the underlying layer. For the same of readability, this patch only introduces the helper framework but doesn't allow the registering code to set its endianness yet. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-12-02migration: stable ram block orderingMichael S. Tsirkin1-0/+3
This makes ram block ordering under migration stable, ordered by offset. This is especially useful for migration to exec, for debugging. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Tested-by: Jason Wang <jasowang@redhat.com>
2010-10-20Export qemu_ram_addr_from_hostMarcelo Tosatti1-1/+2
To be used by next patches. Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Avi Kivity <avi@redhat.com>
2010-08-10Add qemu_ram_alloc_from_ptr functionCam Macdonell1-0/+2
Provide a function to add an allocated region of memory to the qemu RAM. This patch is copied from Marcelo's qemu_ram_map() in qemu-kvm and given the clearer name qemu_ram_alloc_from_ptr(). Signed-off-by: Cam Macdonell <cam@cs.ualberta.ca> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-07-06qemu_ram_alloc: Add DeviceState and name parametersAlex Williamson1-1/+1
These will be used to generate unique id strings for ramblocks. The name field is required, the device pointer is optional as most callers don't have a device. When there's no device or the device isn't a child of a bus implementing BusInfo.get_dev_path, the name should be unique for the platform. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-04-25Remove IO_MEM_SUBWIDTH.Richard Henderson1-1/+0
Greatly simplify the subpage implementation by not supporting multiple devices at the same address at different widths. We don't need full copies of mem_read/mem_write/opaque for each address, only a single index back into the main io_mem_* arrays. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-04-09move targphys.h and hw/poison.h inclusion to cpu-common.hPaolo Bonzini1-0/+8
With more files from outside the hw/ directory being placed into libhw, avoid the need to include hw/hw.h for the sake of targ_phys_addr_t. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-01tcg: initial ia64 supportAurelien Jarno1-1/+1
A few words about design choices: * On IA64, instructions should be grouped by bundle, and dependencies between instructions declared. A first version of this code tried to schedule instructions automatically, but was very complex and too invasive for the current common TCG code (ops not ending at instruction boundaries, code retranslation breaking already generated code, etc.) It was also not very efficient, as dependencies between TCG ops is not available. Instead the option taken by the current implementation does not try to fill the bundle by scheduling instructions, but by providing ops not available as an ia64 instruction, and by offering 22-bit constant loading for most of the instructions. With both options the bundle are filled at approximately the same level. * Up to 128 registers can be affected to a function on IA64, but TCG limits this number to 64, which is actually more than enough. The register affectation is the following: - r0: used to map a constant argument with value 0 - r1: global pointer - r2, r3: internal use - r4 to r6: not used to avoid saving them - r7: env structure - r8 to r11: free for TCG (call clobbered) - r12: stack pointer - r13: thread pointer - r14 to r31: free for TCG (call clobbered) - r32: reserved (return address) - r33: reserved (PFS) - r33 to r63: free for TCG * The IA64 architecture has only 64-bit registers and no 32-bit instructions (the only exception being cmp4). Therefore 64-bit registers and instructions are used for 32-bit ops. The adopted strategy is the same as the ABI, that is the higher 32 bits are undefined. Most ops (and, or, add, shl, etc.) can directly use the 64-bit registers, while some others have to sign-extend (sar, div, etc.) or zero-extend (shr, divu, etc.) the register first. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-21Compile pci only onceBlue Swirl1-0/+11
Move coalesced_mmio declarations to a more accessible location. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-03-12Disable phsyical memory handling in userspace emulation.Paul Brook1-0/+4
Code to handle physical memory access is not meaningful in usrmode emulation, so disable it. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-02-09qemu: memory notifiersMichael S. Tsirkin1-0/+19
This adds notifiers for phys memory changes: a set of callbacks that vhost can register and update kernel accordingly. Down the road, kvm code can be switched to use these as well, instead of calling kvm code directly from exec.c as is done now. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01Revert "Get rid of _t suffix"Anthony Liguori1-34/+34
In the very least, a change like this requires discussion on the list. The naming convention is goofy and it causes a massive merge problem. Something like this _must_ be presented on the list first so people can provide input and cope with it. This reverts commit 99a0949b720a0936da2052cb9a46db04ffc6db29. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01Get rid of _t suffixmalc1-34/+34
Some not so obvious bits, slirp and Xen were left alone for the time being. Signed-off-by: malc <av1474@comtv.ru>
2009-08-25Make CPURead/WriteFunc structure 'const'Blue Swirl1-2/+2
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-24Unbreak large mem support by removing kqemuAnthony Liguori1-5/+0
kqemu introduces a number of restrictions on the i386 target. The worst is that it prevents large memory from working in the default build. Furthermore, kqemu is fundamentally flawed in a number of ways. It relies on the TSC as a time source which will not be reliable on a multiple processor system in userspace. Since most modern processors are multicore, this severely limits the utility of kqemu. kvm is a viable alternative for people looking to accelerate qemu and has the benefit of being supported by the upstream Linux kernel. If someone can implement work arounds to remove the restrictions introduced by kqemu, I'm happy to avoid and/or revert this patch. N.B. kqemu will still function in the 0.11 series but this patch removes it from the 0.12 series. Paul, please Ack or Nack this patch. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-06-16Remove io_index argument from cpu_register_io_memory()Avi Kivity1-2/+1
The parameter is always zero except when registering the three internal io regions (ROM, unassigned, notdirty). Remove the parameter to reduce the API's power, thus facilitating future change. Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-05-19Hardware convenience libraryPaul Brook1-0/+96
The only target dependency for most hardware is sizeof(target_phys_addr_t). Build these files into a convenience library, and use that instead of building for every target. Remove and poison various target specific macros to avoid bogus target dependencies creeping back in. Big/Little endian is not handled because devices should not know or care about this to start with. Signed-off-by: Paul Brook <paul@codesourcery.com>