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2014-09-25cpu-exec: Do CPU_INTERRUPT_HALT unconditionallyRichard Henderson1-5/+0
The signal is currently checked by 10 targets, but only actually raised by Sparc and ARM. For the sake of one test-and-branch, we can handle this generic bit generically. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1410626734-3804-24-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-25target-i386: Use cpu_exec_interrupt qom hookRichard Henderson1-64/+0
Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1410626734-3804-23-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-25target-ppc: Use cpu_exec_interrupt qom hookRichard Henderson1-8/+0
Cc: qemu-ppc@nongnu.org Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1410626734-3804-22-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-25target-lm32: Use cpu_exec_interrupt qom hookRichard Henderson1-7/+0
Cc: Michael Walle <michael@walle.cc> Signed-off-by: Richard Henderson <rth@twiddle.net> Acked-by: Michael Walle <michael@walle.cc> Message-id: 1410626734-3804-21-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-25target-microblaze: Use cpu_exec_interrupt qom hookRichard Henderson1-9/+0
Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1410626734-3804-20-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-25target-mips: Use cpu_exec_interrupt qom hookRichard Henderson1-9/+0
Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Tested-by: Leon Alrae <leon.alrae@imgtec.com> Message-id: 1410626734-3804-19-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-25target-tricore: Remove the dummy interrupt boilerplateRichard Henderson1-5/+0
It can go back in when it actually does something. Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-id: 1410626734-3804-18-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-25target-openrisc: Use cpu_exec_interrupt qom hookRichard Henderson1-18/+0
Cc: Jia Liu <proljc@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Tested-by: Jia Liu <proljc@gmail.com> Message-id: 1410626734-3804-17-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-25target-sparc: Use cpu_exec_interrupt qom hookRichard Henderson1-16/+0
Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1410626734-3804-16-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-25target-arm: Use cpu_exec_interrupt qom hookRichard Henderson1-23/+0
Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1410626734-3804-15-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-25target-unicore32: Use cpu_exec_interrupt qom hookRichard Henderson1-7/+0
Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1410626734-3804-14-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-25target-sh4: Use cpu_exec_interrupt qom hookRichard Henderson1-5/+0
Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1410626734-3804-13-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-25target-alpha: Use cpu_exec_interrupt qom hookRichard Henderson1-32/+0
Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1410626734-3804-12-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-25target-cris: Use cpu_exec_interrupt qom hookRichard Henderson1-21/+0
Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1410626734-3804-11-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-25target-m68k: Use cpu_exec_interrupt qom hookRichard Henderson1-13/+0
Since do_interrupt_m68k_hardirq is no longer used outside op_helper.c, make it static. Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1410626734-3804-10-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-25target-s390x: Use cpu_exec_interrupt qom hookRichard Henderson1-6/+0
Cc: Alexander Graf <agraf@suse.de> Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1410626734-3804-9-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-25target-xtensa: Use cpu_exec_interrupt qom hookRichard Henderson1-6/+0
Cc: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Max Filippov <jcmvbkbc@gmail.com> Message-id: 1410626734-3804-8-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-25qom: Add cpu_exec_interrupt hookRichard Henderson1-5/+9
Continuing the removal of ifdefs from cpu_exec. Cc: Andreas Färber <afaerber@suse.de> Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1410626734-3804-7-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-25target-ppc: Use cpu_exec_enter qom hookRichard Henderson1-3/+0
Cc: qemu-ppc@nongnu.org Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1410626734-3804-6-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-25target-m68k: Use cpu_exec_enter/exit qom hooksRichard Henderson1-12/+1
Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1410626734-3804-5-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-25target-i386: Use cpu_exec_enter/exit qom hooksRichard Henderson1-12/+2
Note that the code that was within the "exit" ifdef block was identical to the cpu_compute_eflags inline, so make that simplification at the same time. Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1410626734-3804-4-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-25cpu-exec: Remove do-nothing ifdef chainsRichard Henderson1-32/+0
Around the cpu_exec_enter/exit hooks contain many empty ifdef blocks. Delete all of these to highlight those targets for which we actually need to do work. Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1410626734-3804-3-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-25qom: Add cpu_exec_enter and cpu_exec_exit hooksRichard Henderson1-7/+2
In preparation for removing a bunch of ifdefs from cpu_exec. Cc: Andreas Färber <afaerber@suse.de> Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1410626734-3804-2-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-12cpu-exec: Make debug_excp_handler a QOM CPU methodPeter Maydell1-10/+3
Make the debug_excp_handler target specific hook into a QOM CPU method. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-12cpu-exec.c: Allow disabling of IRQs on ARM Cortex-M CPUsDavid Hoover1-2/+2
Correct an error in the logic for deciding whether we can take an IRQ interrupt which meant that on M profile cores it was never possible to disable them. The design here is still bogus in that M profile doesn't have separate "IRQ" and "FIQ", which are an A/R profile concept; we should ideally implement the proper priority based scheme. Signed-off-by: David Hoover <spm@boiteauxlettres.sent.at> [PMM: Wrote a proper commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-01target-tricore: Add target stubs and qom-cpuBastian Koppelmann1-1/+10
Add TriCore target stubs, and QOM cpu, and Maintainer Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-id: 1409572800-4116-2-git-send-email-kbastian@mail.uni-paderborn.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-12trace: add some tcg tracing supportAlex Bennée1-0/+6
This adds a couple of tcg specific trace-events which are useful for tracing execution though tcg generated blocks. It's been tested with lttng user space tracing but is generic enough for all systems. The tcg events are: * translate_block - when a subject block is translated * exec_tb - when a translated block is entered * exec_tb_exit - when we exit the translated code * exec_tb_nocache - special case translations Of course we can only trace the entrance to the first block of a chain as each block will jump directly to the next when it can. See the -d nochain patch to allow more complete tracing at the expense of performance. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-08-07monitor: Add drift info to 'info jit'Sebastian Tanase1-0/+6
Show in 'info jit' the current delay between the host clock and the guest clock. In addition, print the maximum advance and delay of the guest compared to the host. Signed-off-by: Sebastian Tanase <sebastian.tanase@openwide.fr> Tested-by: Camille Bégué <camille.begue@openwide.fr> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-08-06cpu-exec: Print to console if the guest is lateSebastian Tanase1-1/+32
If the align option is enabled, we print to the user whenever the guest clock is behind the host clock in order for he/she to have a hint about the actual performance. The maximum print interval is 2s and we limit the number of messages to 100. If desired, this can be changed in cpu-exec.c Signed-off-by: Sebastian Tanase <sebastian.tanase@openwide.fr> Tested-by: Camille Bégué <camille.begue@openwide.fr> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-08-06cpu-exec: Add sleeping algorithmSebastian Tanase1-0/+79
The goal is to sleep qemu whenever the guest clock is in advance compared to the host clock (we use the monotonic clocks). The amount of time to sleep is calculated in the execution loop in cpu_exec. At first, we tried to approximate at each for loop the real time elapsed while searching for a TB (generating or retrieving from cache) and executing it. We would then approximate the virtual time corresponding to the number of virtual instructions executed. The difference between these 2 values would allow us to know if the guest is in advance or delayed. However, the function used for measuring the real time (qemu_clock_get_ns(QEMU_CLOCK_REALTIME)) proved to be very expensive. We had an added overhead of 13% of the total run time. Therefore, we modified the algorithm and only take into account the difference between the 2 clocks at the begining of the cpu_exec function. During the for loop we try to reduce the advance of the guest only by computing the virtual time elapsed and sleeping if necessary. The overhead is thus reduced to 3%. Even though this method still has a noticeable overhead, it no longer is a bottleneck in trying to achieve a better guest frequency for which the guest clock is faster than the host one. As for the the alignement of the 2 clocks, with the first algorithm the guest clock was oscillating between -1 and 1ms compared to the host clock. Using the second algorithm we notice that the guest is 5ms behind the host, which is still acceptable for our use case. The tests where conducted using fio and stress. The host machine in an i5 CPU at 3.10GHz running Debian Jessie (kernel 3.12). The guest machine is an arm versatile-pb built with buildroot. Currently, on our test machine, the lowest icount we can achieve that is suitable for aligning the 2 clocks is 6. However, we observe that the IO tests (using fio) are slower than the cpu tests (using stress). Signed-off-by: Sebastian Tanase <sebastian.tanase@openwide.fr> Tested-by: Camille Bégué <camille.begue@openwide.fr> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-05-13cpu: make CPU_INTERRUPT_RESET available on all targetsPaolo Bonzini1-10/+13
On the x86, some devices need access to the CPU reset pin (INIT#). Provide a generic service to do this, using one of the internal cpu_interrupt targets. Generalize the PPC-specific code for CPU_INTERRUPT_RESET to other targets. Since PPC does not support migration across QEMU versions (its machine types are not versioned yet), I picked the value that is used on x86, CPU_INTERRUPT_TGT_INT_1. Consequently, TGT_INT_2 and TGT_INT_3 are shifted down by one while keeping their value. Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-04-04cpu-exec: Unlock tb_lock if we longjmp out of code generationPeter Maydell1-0/+8
If the guest attempts to execute from unreadable memory, this will cause us to longjmp back to the main loop from inside the target frontend decoder. For linux-user mode, this means we will still hold the tb_ctx.tb_lock, and will deadlock when we try to start executing code again. Unlock the lock in the return-from-longjmp code path to avoid this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andrei Warkentin <andrey.warkentin@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-03-13cpu-exec: Change cpu_resume_from_signal() argument to CPUStateAndreas Färber1-3/+1
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13translate-all: Change tb_gen_code() argument to CPUStateAndreas Färber1-2/+2
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu-exec: Change cpu_loop_exit() argument to CPUStateAndreas Färber1-8/+6
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Move watchpoint fields from CPU_COMMON to CPUStateAndreas Färber1-2/+3
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Move exception_index field from CPU_COMMON to CPUStateAndreas Färber1-25/+25
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Move jmp_env field from CPU_COMMON to CPUStateAndreas Färber1-3/+5
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Move tb_jmp_cache field from CPU_COMMON to CPUStateAndreas Färber1-2/+4
Clear it on reset. Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Move icount_decr field from CPU_COMMON to CPUStateAndreas Färber1-2/+2
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Move icount_extra field from CPU_COMMON to CPUStateAndreas Färber1-5/+5
Reset it. Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-13cpu: Turn cpu_has_work() into a CPUClass hookAndreas Färber1-5/+0
Default to false. Tidy variable naming and inline cast uses while at it. Tested-by: Jia Liu <proljc@gmail.com> (or32) Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-02-26target-arm: Store AIF bits in env->pstate for AArch32Peter Maydell1-2/+2
To avoid complication in code that otherwise would not need to care about whether EL1 is AArch32 or AArch64, we should store the interrupt mask bits (CPSR.AIF in AArch32 and PSTATE.DAIF in AArch64) in one place consistently regardless of EL1's mode. Since AArch64 has an extra enable bit (D for debug exceptions) which isn't visible in AArch32, this means we need to keep the enables in env->pstate. (This is also consistent with the general approach we're taking that we handle 32 bit CPUs as being like AArch64/ARMv8 CPUs but which only run in 32 bit mode.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-11exec: Make ldl_*_phys input an AddressSpaceEdgar E. Iglesias1-1/+4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-01-10Merge remote-tracking branch 'afaerber/tags/qom-cpu-for-anthony' into stagingAnthony Liguori1-4/+10
QOM CPUState refactorings / X86CPU * TLB invalidation optimizations * X86CPU initialization cleanups * Preparations for X86CPU hot-unplug # gpg: Signature made Tue 24 Dec 2013 04:51:52 AM PST using RSA key ID 3E7E013F # gpg: Good signature from "Andreas Färber <afaerber@suse.de>" # gpg: aka "Andreas Färber <afaerber@suse.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 174F 0347 1BCC 221A 6175 6F96 FA2E D12D 3E7E 013F * afaerber/tags/qom-cpu-for-anthony: target-i386: Cleanup 'foo=val' feature handling target-i386: Cleanup 'foo' feature handling target-i386: Convert 'check' and 'enforce' to static properties target-i386: Convert 'hv_spinlocks' to static property target-i386: Convert 'hv_vapic' to static property target-i386: Convert 'hv_relaxed' to static property cpu-exec: Optimize X86CPU usage in cpu_exec() target-i386: Move apic_state field from CPUX86State to X86CPU cputlb: Tidy memset() of arrays cputlb: Use memset() when flushing entries
2014-01-07exec: Delay CPU_LOG_TB_CPU until we actually execute a TBRichard Henderson1-17/+19
The previous placement could result in duplicate logging while still processing interrupts. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-12-24cpu-exec: Optimize X86CPU usage in cpu_exec()Andreas Färber1-4/+10
Replace growing numbers of inline x86_env_get_cpu() with x86_cpu variable. Reviewed-by: Chen Fan <chen.fan@cn.fujitsu.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-12-23target-i386: Move apic_state field from CPUX86State to X86CPUChen Fan1-1/+1
This motion is preparing for refactoring vCPU APIC subsequently. Signed-off-by: Chen Fan <chen.fan.fnst@cn.fujitsu.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-10-07cpu-exec: Also reload CPUClass *cc after longjmp return in cpu_exec()Juergen Lock1-0/+4
Local variable CPUClass *cc needs to be reloaded after return from longjmp, too. (This fixes a mips-softmmu crash observed on FreeBSD when QEMU is built with clang.) Reported-by: Dimitry Andric <dim@FreeBSD.org> Signed-off-by: Juergen Lock <nox@jelal.kn-bremen.de> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-09-02tcg: Fix next_tb type in cpu_execRichard Henderson1-1/+1
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
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