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2014-02-11exec: Make cpu_memory_rw_debug use the CPUs ASEdgar E. Iglesias1-5/+5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make cpu_physical_memory_write_rom input an ASEdgar E. Iglesias1-7/+8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make stb_phys input an AddressSpaceEdgar E. Iglesias1-3/+3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make stw_*_phys input an AddressSpaceEdgar E. Iglesias1-10/+10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make stl_phys_notdirty input an AddressSpaceEdgar E. Iglesias1-2/+2
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make stl_*_phys input an AddressSpaceEdgar E. Iglesias1-9/+10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make stq_*_phys input an AddressSpaceEdgar E. Iglesias1-6/+6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make lduw_*_phys input an AddressSpaceEdgar E. Iglesias1-9/+9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make ldq/ldub_*_phys input an AddressSpaceEdgar E. Iglesias1-11/+11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make ldl_*_phys input an AddressSpaceEdgar E. Iglesias1-10/+9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: On AS changes, only flush affected CPU TLBsEdgar E. Iglesias1-0/+5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11cpu: Add per-cpu address spaceEdgar E. Iglesias1-8/+19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make memory_region_section_get_iotlb use section ASEdgar E. Iglesias1-1/+1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Always initialize MemorySection address spacesEdgar E. Iglesias1-0/+2
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make iotlb_to_region input an ASEdgar E. Iglesias1-3/+2
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-11exec: Make tb_invalidate_phys_addr input an ASEdgar E. Iglesias1-1/+2
No functional change. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-02-10memory: fix limiting of translation at a page boundaryPaolo Bonzini1-16/+19
Commit 360e607 (address_space_translate: do not cross page boundaries, 2014-01-30) broke MMIO accesses in cases where the section is shorter than the full register width. This can happen for example with the Bochs DISPI registers, which are 16 bits wide but have only a 1-byte long MemoryRegion (if you write to the "second byte" of the register your access is discarded; it doesn't write only to half of the register). Restrict the action of commit 360e607 to direct RAM accesses. This is enough for Xen, since MMIO will not go through the mapcache. Reported-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Cc: qemu-stable@nongnu.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-01-30address_space_translate: do not cross page boundariesStefano Stabellini1-2/+4
The following commit: commit 149f54b53b7666a3facd45e86eece60ce7d3b114 Author: Paolo Bonzini <pbonzini@redhat.com> Date: Fri May 24 12:59:37 2013 +0200 memory: add address_space_translate breaks Xen support in QEMU, in particular the Xen mapcache. The effect is that one Windows XP installation out of ten would end up with BSOD. The reason is that after this commit l in address_space_rw can span a page boundary, however qemu_get_ram_ptr still calls xen_map_cache asking to map a single page (if block->offset == 0). Fix the issue by reverting to the previous behaviour: do not return a length from address_space_translate_internal that can span a page boundary. Also in address_space_translate do not ignore the length returned by address_space_translate_internal. This patch should be backported to QEMU 1.6.x. Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Signed-off-by: Anthony Perard <anthony.perard@citrix.com> Tested-by: Paolo Bonzini <pbonzini@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Cc: qemu-stable@nongnu.org
2014-01-24Merge remote-tracking branch 'qemu-kvm/uq/master' into stagingAnthony Liguori1-1/+1
* qemu-kvm/uq/master: kvm: always update the MPX model specific register KVM: fix addr type for KVM_IOEVENTFD KVM: Retry KVM_CREATE_VM on EINTR mempath prefault: fix off-by-one error kvm: x86: Separately write feature control MSR on reset roms: Flush icache when writing roms to guest memory target-i386: clear guest TSC on reset target-i386: do not special case TSC writeback target-i386: Intel MPX Conflicts: exec.c aliguori: fix trivial merge conflict in exec.c Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2014-01-13memory: split cpu_physical_memory_* functions to its own includeJuan Quintela1-0/+1
All the functions that use ram_addr_t should be here. Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Orit Wasserman <owasserm@redhat.com>
2014-01-13memory: cpu_physical_memory_set_dirty_tracking() should return voidJuan Quintela1-6/+4
Result was always 0, and not used anywhere. Once there, use bool type for the parameter. Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Orit Wasserman <owasserm@redhat.com>
2014-01-13memory: make cpu_physical_memory_reset_dirty() take a length parameterJuan Quintela1-11/+8
We have an end parameter in all the callers, and this make it coherent with the rest of cpu_physical_memory_* functions, that also take a length parameter. Once here, move the start/end calculation to tlb_reset_dirty_range_all() as we don't need it here anymore. Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Orit Wasserman <owasserm@redhat.com>
2014-01-13memory: s/dirty/clean/ in cpu_physical_memory_is_dirty()Juan Quintela1-3/+3
All uses except one really want the other meaning. Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Orit Wasserman <owasserm@redhat.com>
2014-01-13memory: s/mask/clear/ cpu_physical_memory_mask_dirty_rangeJuan Quintela1-1/+1
Now all functions use the same wording that bitops/bitmap operations Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Orit Wasserman <owasserm@redhat.com>
2014-01-13memory: split dirty bitmap into threeJuan Quintela1-3/+6
After all the previous patches, spliting the bitmap gets direct. Note: For some reason, I have to move DIRTY_MEMORY_* definitions to the beginning of memory.h to make compilation work. Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Orit Wasserman <owasserm@redhat.com>
2014-01-13memory: only resize dirty bitmap when memory size increasesJuan Quintela1-3/+9
Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Orit Wasserman <owasserm@redhat.com>
2014-01-13memory: cpu_physical_memory_mask_dirty_range() always clears a single flagJuan Quintela1-9/+10
Document it Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Orit Wasserman <owasserm@redhat.com>
2014-01-13memory: cpu_physical_memory_set_dirty_range() always dirty all flagsJuan Quintela1-1/+1
So remove the flag argument and do it directly. After this change, there is nothing else using cpu_physical_memory_set_dirty_flags() so remove it. Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Orit Wasserman <owasserm@redhat.com>
2014-01-13memory: set single dirty flags when possibleJuan Quintela1-3/+4
Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Orit Wasserman <owasserm@redhat.com>
2014-01-13memory: make cpu_physical_memory_is_dirty return boolJuan Quintela1-5/+2
Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Orit Wasserman <owasserm@redhat.com>
2014-01-13exec: create function to get a single dirty bitJuan Quintela1-1/+1
Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Orit Wasserman <owasserm@redhat.com>
2014-01-13exec: use accessor function to know if memory is dirtyJuan Quintela1-1/+1
Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Orit Wasserman <owasserm@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
2013-12-30mempath prefault: fix off-by-one errorMarcelo Tosatti1-1/+1
Fix off-by-one error (noticed by Andrea Arcangeli). Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2013-12-20roms: Flush icache when writing roms to guest memoryAlexander Graf1-5/+39
We use the rom infrastructure to write firmware and/or initial kernel blobs into guest address space. So we're basically emulating the cache off phase on very early system bootup. That phase is usually responsible for clearing the instruction cache for anything it writes into cachable memory, to ensure that after reboot we don't happen to execute stale bits from the instruction cache. So we need to invalidate the icache every time we write a rom into guest address space. We do not need to do this for every DMA since the guest expects it has to flush the icache manually in that case. This fixes random reboot issues on e5500 (booke ppc) for me. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-13roms: Flush icache when writing roms to guest memoryAlexander Graf1-5/+39
We use the rom infrastructure to write firmware and/or initial kernel blobs into guest address space. So we're basically emulating the cache off phase on very early system bootup. That phase is usually responsible for clearing the instruction cache for anything it writes into cachable memory, to ensure that after reboot we don't happen to execute stale bits from the instruction cache. So we need to invalidate the icache every time we write a rom into guest address space. We do not need to do this for every DMA since the guest expects it has to flush the icache manually in that case. This fixes random reboot issues on e5500 (booke ppc) for me. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-12-11exec: separate sections and nodes per address spaceMarcel Apfelbaum1-89/+66
Every address space has its own nodes and sections, but it uses the same global arrays of nodes/section. This limits the number of devices that can be attached to the guest to 20-30 devices. It happens because: - The sections array is limited to 2^12 entries. - The main memory has at least 100 sections. - Each device address space is actually an alias to main memory, multiplying its number of nodes/sections. Remove the limitation by using separate arrays of nodes and sections for each address space. Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-10exec: reduce L2_PAGE_SIZEMichael S. Tsirkin1-1/+1
With the single exception of ppc with 16M pages, we get the same number of levels with L2_PAGE_SIZE = 10 as with L2_PAGE_SIZE = 9. by doing this we reduce memory footprint of a single level in the node memory map by 2x without runtime overhead. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-10exec: make address spaces 64-bit widePaolo Bonzini1-6/+2
As an alternative to commit 818f86b (exec: limit system memory size, 2013-11-04) let's just make all address spaces 64-bit wide. This eliminates problems with phys_page_find ignoring bits above TARGET_PHYS_ADDR_SPACE_BITS and address_space_translate_internal consequently messing up the computations. In Luiz's reported crash, at startup gdb attempts to read from address 0xffffffffffffffe6 to 0xffffffffffffffff inclusive. The region it gets is the newly introduced master abort region, which is as big as the PCI address space (see pci_bus_init). Due to a typo that's only 2^63-1, not 2^64. But we get it anyway because phys_page_find ignores the upper bits of the physical address. In address_space_translate_internal then diff = int128_sub(section->mr->size, int128_make64(addr)); *plen = int128_get64(int128_min(diff, int128_make64(*plen))); diff becomes negative, and int128_get64 booms. The size of the PCI address space region should be fixed anyway. Reported-by: Luiz Capitulino <lcapitulino@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-10exec: memory radix tree page level compressionMichael S. Tsirkin1-1/+74
At the moment, memory radix tree is already variable width, but it can only skip the low bits of address. This is efficient if we have huge memory regions but inefficient if we are only using a tiny portion of the address space. After we have built up the map, detect configurations where a single L2 entry is valid. We then speed up the lookup by skipping one or more levels. In case any levels were skipped, we might end up in a valid section instead of erroring out. We handle this by checking that the address is in range of the resulting section. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-10exec: pass hw address to phys_page_findMichael S. Tsirkin1-4/+4
callers always shift by target page bits so let's just do this internally. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-10exec: extend skip field to 6 bit, page entry to 32 bitMichael S. Tsirkin1-6/+6
Extend skip to 6 bit. As page entry doesn't fit in 16 bit any longer anyway, extend it to 32 bit. This doubles node map memory requirements, but follow-up patches will save this memory. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-10exec: replace leaf with skipMichael S. Tsirkin1-8/+9
In preparation for dynamic radix tree depth support, rename is_leaf field to skip, telling us how many bits to skip to next level. Set to 0 for leaf. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-10split definitions for exec.c and translate-all.c radix treesPaolo Bonzini1-8/+21
The exec.c and translate-all.c radix trees are quite different, and the exec.c one in particular is not limited to the CPU---it can be used also by devices that do DMA, and in that case the address space is not limited to TARGET_PHYS_ADDR_SPACE_BITS bits. We want to make exec.c's radix trees 64-bit wide. As a first step, stop sharing the constants between exec.c and translate-all.c. exec.c gets P_L2_* constants, translate-all.c gets V_L2_*, for consistency with the existing V_L1_* symbols. Though actually in the softmmu case translate-all.c is also indexed by physical addresses... This patch has no semantic change. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-11-25qemu: mempath: prefault pages manually (v4)Marcelo Tosatti1-12/+47
v4: s/fail/failed/ (Peter Maydell) Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2013-11-13Merge remote-tracking branch 'mst/tags/for_anthony' into stagingAnthony Liguori1-6/+1
pci, pc, virtio bug fixes This reverts PCI master abort support - we'll want it eventually but it exposes too many core bugs to be safe for 1.7. This also reverts a recent exec.c change that was an attempt to work-around some of these core bugs. Also included are small fixes in pc and virtio, and a core loader fix for PPC bamboo. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Sun 10 Nov 2013 05:13:22 AM PST using RSA key ID D28D5469 # gpg: Can't check signature: public key not found # By Michael S. Tsirkin (3) and others # Via Michael S. Tsirkin * mst/tags/for_anthony: Revert "exec: limit system memory size" Revert "hw/pci: partially handle pci master abort" loader: drop return value for rom_add_blob_fixed acpi-build: disable with -no-acpi virtio-net: only delete bh that existed Fix pc migration from qemu <= 1.5 Message-id: 1384159176-31662-1-git-send-email-mst@redhat.com Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-11-10Revert "exec: limit system memory size"Michael S. Tsirkin1-6/+1
This reverts commit 818f86b88394b7b2b59d313e51043fe15a8004db. This was a work-around for bugs elsewhere in the system, exposed by commit a53ae8e934cd54686875b5bcfc2f434244ee55d6: "hw/pci: partially handle pci master abort" since that's reverted now, the work-around is not required for 1.7 anymore. The proper fix is supporting full 64 bit addresses in the radix tree. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Tested-by: Marcel Apfelbaum <marcel.a@redhat.com>
2013-11-08exec: fix breakpoint_invalidate when pc may not be translatedMax Filippov1-2/+4
This fixes qemu abort with the following message: include/qemu/int128.h:22: int128_get64: Assertion `!a.hi' failed. which happens due to attempt to invalidate breakpoint by virtual address for which get_phys_page_debug couldn't find mapping. For more details see http://lists.nongnu.org/archive/html/qemu-devel/2013-09/msg04582.html Cc: qemu-stable@nongnu.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
2013-11-04exec: limit system memory sizeMichael S. Tsirkin1-1/+6
The page table logic in exec.c assumes that memory addresses are at most TARGET_PHYS_ADDR_SPACE_BITS. But pci addresses are full 64 bit so if we try to render them ignoring the extra bits, we get strange effects with sections overlapping each other. To fix, simply limit the system memory size to 1 << TARGET_PHYS_ADDR_SPACE_BITS, pci addresses will be rendered within that. Cc: qemu-stable@nongnu.org Reported-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-10-28exec: Fix bounce buffer allocation in address_space_map()Kevin Wolf1-1/+3
This fixes a regression introduced by commit e3127ae0c, which kept the allocation size of the bounce buffer limited to one page in order to avoid unbounded allocations (as explained in the commit message of 6d16c2f88), but broke the reporting of the shortened bounce buffer to the caller. The caller therefore assumes that the full requested size was provided and causes memory corruption when writing beyond the end of the actually allocated buffer. Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2013-10-17exec: remove qemu_safe_ram_ptrPaolo Bonzini1-69/+28
This is not needed since the RAM list is not modified anymore by qemu_get_ram_ptr. Replace it with qemu_get_ram_block. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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