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2014-03-10pxa2xx: Don't shift into sign bitPeter Maydell1-3/+3
Add missing 'U' suffixes to avoid potentially shifting into the sign bit of a signed integer. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1392988008-15938-2-git-send-email-peter.maydell@linaro.org
2014-02-26target-arm: Store AIF bits in env->pstate for AArch32Peter Maydell1-2/+2
To avoid complication in code that otherwise would not need to care about whether EL1 is AArch32 or AArch64, we should store the interrupt mask bits (CPSR.AIF in AArch32 and PSTATE.DAIF in AArch64) in one place consistently regardless of EL1's mode. Since AArch64 has an extra enable bit (D for debug exceptions) which isn't visible in AArch32, this means we need to keep the enables in env->pstate. (This is also consistent with the general approach we're taking that we handle 32 bit CPUs as being like AArch64/ARMv8 CPUs but which only run in 32 bit mode.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-26target-arm: Implement AArch64 TTBR*Peter Maydell1-1/+1
Implement the AArch64 TTBR* registers. For v7 these were already 64 bits to handle LPAE, but implemented as two separate uint32_t fields. Combine them into a single uint64_t which can be used for all purposes. Since this requires touching every use, take the opportunity to rename the field to the architectural name. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-21Merge remote-tracking branch ↵Peter Maydell1-23/+13
'remotes/pmaydell/tags/pull-target-arm-20140220' into staging target-arm queue: * Fix a bug causing an assertion in the NVIC on ARMv7M models * More A64 Neon instructions * Refactor cpreg API to separate out access check functions, as groundwork for AArch64 system mode * Fix bug in linux-user A64 store-exclusive of XZR # gpg: Signature made Thu 20 Feb 2014 11:12:57 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20140220: (30 commits) linux-user: AArch64: Fix exclusive store of the zero register target-arm: A64: Implement unprivileged load/store target-arm: A64: Implement narrowing three-reg-diff operations target-arm: A64: Implement the wide 3-reg-different operations target-arm: A64: Add most remaining three-reg-diff widening ops target-arm: A64: Add opcode comments to disas_simd_three_reg_diff target-arm: A64: Implement store-exclusive for system mode target-arm: Fix incorrect type for value argument to write_raw_cp_reg target-arm: Remove failure status return from read/write_raw_cp_reg target-arm: Remove unnecessary code now read/write fns can't fail target-arm: Drop success/fail return from cpreg read and write functions target-arm: Convert miscellaneous reginfo structs to accessfn target-arm: Convert generic timer reginfo to accessfn target-arm: Convert performance monitor reginfo to accessfn target-arm: Split cpreg access checks out from read/write functions target-arm: Stop underdecoding ARM946 PRBS registers target-arm: Log bad system register accesses with LOG_UNIMP target-arm: Remove unused ARMCPUState sr substruct target-arm: Restrict check_ap() use of S and R bits to v6 and earlier target-arm: Define names for SCTLR bits ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-20target-arm: Drop success/fail return from cpreg read and write functionsPeter Maydell1-23/+13
All cpreg read and write functions now return 0, so we can clean up their prototypes: * write functions return void * read functions return the value rather than taking a pointer to write the value to This is a fairly mechanical change which makes only the bare minimum set of changes to the callers of read and write functions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-02-14pxa2xx: QOM'ify I2C slaveAndreas Färber1-13/+25
Replace usages of FROM_I2C_SLAVE() and direct parent field accesses with QOM cast macro. Rename parent field to assure we caught all. Reuse type constant in pxa2xx_i2c_init(). Add some missing braces while at it. Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-02-14i2c: Rename i2c_bus to I2CBusAndreas Färber1-3/+3
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-02-04vmstate: Make VMSTATE_STRUCT_POINTER take type, not ptr-to-typePeter Maydell1-1/+1
The VMSTATE_STRUCT_POINTER macros are a bit odd in that they must be passed an argument "FooType *" rather than just taking the FooType. They're only used in one place, so it's easy to tidy this up. This also lets us use the macro to replace the hand-rolled VMSTATE_PTIMER. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Juan Quintela <quintela@redhat.com>
2013-08-22aio / timers: Switch entire codebase to the new timer APIAlex Bligh1-13/+13
This is an autogenerated patch using scripts/switch-timer-api. Switch the entire code base to using the new timer API. Note this patch may introduce some line length issues. Signed-off-by: Alex Bligh <alex@alex.org.uk> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-08-22aio / timers: Convert rtc_clock to be a QEMUClockTypeAlex Bligh1-16/+19
Convert rtc_clock to be a QEMUClockType Move rtc_clock users to use the new API Signed-off-by: Alex Bligh <alex@alex.org.uk> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-08-05pxa2xx: Avoid object_get_link_property() assertion for "parent_bus"Andreas Färber1-1/+3
pxa2xx_i2c_init() creates a pxa2xx-i2c-slave device on a second i2c-bus, which has a NULL parent device. This causes an assertion in object_get_canonical_path() when accessing pxa2xx-i2c-slave's "parent_bus" link<bus> property in tosa and likely other PXA2xx machines. Fix this by using the pxa2xx_i2c device, created just before, as parent. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Message-id: 1375621501-5564-1-git-send-email-afaerber@suse.de Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-29pxa2xx: QOM cast cleanup for PXA2xxI2CStateAndreas Färber1-13/+21
Introduce a type constant, use QOM casts, rename the parent field and prepare for QOM realize. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29pxa2xx: QOM cast cleanup for PXA2xxRTCStateAndreas Färber1-5/+12
Introduce a type constant, use QOM casts and rename the parent field. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29pxa2xx: QOM cast cleanup for PXA2xxSSPStateAndreas Färber1-10/+18
Introduce a type constant, use QOM casts, rename the parent field and prepare for QOM realize. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-09cpu: Replace cpu_single_env with CPUState current_cpuAndreas Färber1-2/+1
Move it to qom/cpu.h. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-04hw/a*: pass owner to memory_region_init* functionsPaolo Bonzini1-4/+6
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-07-04memory: add owner argument to initialization functionsPaolo Bonzini1-15/+15
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-04-15sysemu: avoid proliferation of include/ subdirectoriesPaolo Bonzini1-1/+1
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-04-08hw: move headers to include/Paolo Bonzini1-3/+3
Many of these should be cleaned up with proper qdev-/QOM-ification. Right now there are many catch-all headers in include/hw/ARCH depending on cpu.h, and this makes it necessary to compile these files per-target. However, fixing this does not belong in these patches. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-04-04qemu-char: Call fe_claim / fe_release when not using qdev chr propertiesHans de Goede1-1/+3
chardev-frontends need to explictly check, increase and decrement the avail_connections "property" of the chardev when they are not using a qdev-chardev-property for the chardev. This fixes things like: qemu-kvm -chardev stdio,id=foo -device isa-serial,chardev=foo \ -mon chardev=foo Working, where they should fail. Most of the changes here are due to old hardware emulation code which is using serial_hds directly rather then a qdev-chardev-property. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Message-id: 1364412581-3672-3-git-send-email-hdegoede@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-03-12cpu: Pass CPUState to cpu_interrupt()Andreas Färber1-3/+4
Move it to qom/cpu.h to avoid issues with include order. Change pc_acpi_smi_interrupt() opaque to X86CPU. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-03-01arm: move files referencing CPU to hw/arm/Paolo Bonzini1-0/+2291
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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