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2013-01-10Make all static TypeInfos constAndreas Färber1-1/+1
Since 39bffca2030950ef6efe57c2fac8327a45ae1015 (qdev: register all types natively through QEMU Object Model), TypeInfo as used in the common, non-iterative pattern is no longer amended with information and should therefore be const. Fix the documented QOM examples: sed -i 's/static TypeInfo/static const TypeInfo/g' include/qom/object.h Since frequently the wrong examples are being copied by contributors of new devices, fix all types in the tree: sed -i 's/^static TypeInfo/static const TypeInfo/g' */*.c sed -i 's/^static TypeInfo/static const TypeInfo/g' */*/*.c This also avoids to piggy-back these changes onto real functional changes or other refactorings. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-12-18arm_gic: Add cpu nr to Raised IRQ messagePeter Crosthwaite1-1/+1
Add the relevant CPU nr to this debug message to make IRQ debugging more informative. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-12-11hw/arm_gic: fix target CPUs affected by set enable/pending opsDaniel Sangorrin1-2/+3
Fix a bug on the ARM GIC model where interrupts are not set pending on the correct target CPUs when they are triggered by writes to the Interrupt Set Enable or Set Pending registers. Signed-off-by: Daniel Sangorrin <dsl@ertl.jp> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-12-11hw/arm_gic: Fix comparison with priority mask registerPeter Maydell1-1/+1
The GIC spec states that only interrupts with higher priority than the value in the GICC_PMR priority mask register are passed through to the processor. We were incorrectly allowing through interrupts with a priority equal to the specified value: correct the comparison operation to match the spec. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Igor Mitsyanko <i.mitsyanko@samsung.com>
2012-10-30hw/arm_gic: Use LOG_GUEST_ERRORPeter Maydell1-4/+8
Use LOG_GUEST_ERROR to report guest accesses to bad offsets. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-23Rename target_phys_addr_t to hwaddrAvi Kivity1-10/+10
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are reserved) and its purpose doesn't match the name (most target_phys_addr_t addresses are not target specific). Replace it with a finger-friendly, standards conformant hwaddr. Outstanding patchsets can be fixed up with the command git rebase -i --exec 'find -name "*.[ch]" | xargs s/target_phys_addr_t/hwaddr/g' origin Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-10-12arm_gic: Rename gic_state to GICStatePeter Maydell1-22/+22
Rename the gic_state struct to match QEMU's coding style conventions for structure names, since the impending KVM-for-ARM patches will create another subclass of it. This patch was created using: sed -i 's/gic_state/GICState/g' hw/arm_gic.c hw/arm_gic_common.c \ hw/arm_gic_internal.h hw/armv7m_nvic.c Acked-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-12hw/arm_gic.c: Fix improper DPRINTF output.Evgeny Voevodin1-1/+1
s->cpu_enabled is an array, so s->cpu_enabled ? "En" : "Dis" returns "En" always. We should use s->cpu_enabled[cpu] here. Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-08-29hw/arm_gic.c: Define .class_size in arm_gic_info TypeInfoPeter Maydell1-0/+1
Add the missing .class_size definition to the arm_gic_info TypeInfo. This fixes the memory corruption and possible segfault that otherwise results when the class struct is allocated at too small a size and the class init function writes off the end of it. Reported-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-06-26Merge remote-tracking branch 'stefanha/trivial-patches' into stagingAnthony Liguori1-1/+1
* stefanha/trivial-patches: tci: Support INDEX_op_bswap64_i64 target-i386: Use QEMU instead of Qemu Makefile.hw: avoid overly large 'make clean' rm command configure: Fix typo arm_gic: Send dbg msgs to stderr not stdout checkpatch: Add QEMU specific rule qemu-config: Use QEMU instead of Qemu libqtest: Fix socket_accept() to pass address_len Makefile.user: Define CONFIG_USER_ONLY for libuser/ Makefile: Remove macro qapi-dir Makefile: Remove BUILD_DIR from qapi-dir Install 'bepo' keymap already included in Qemu source
2012-06-22arm_gic: Send dbg msgs to stderr not stdoutPeter A. G. Crosthwaite1-1/+1
Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2012-06-19hw/armv7m_nvic: Make the NVIC a freestanding classPeter Maydell1-227/+14
Rearrange the GIC and NVIC so both are straightforward subclasses of a common class, rather than having the NVIC source file textually include arm_gic.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-19hw/arm_gic: Move CPU interface memory region setup into arm_gic_initPeter Maydell1-13/+13
Remove more NVIC ifdefs by moving the code to setup the CPU interface memory regions into the GIC specific arm_gic_init() function rather than the gic_init() function. Rename the latter to more closely reflect what it's now actually doing. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-19hw/arm_gic.c: Make NVIC interrupt numbering a runtime settingPeter Maydell1-8/+4
Make the minor tweaks to interrupt numbering used by the NVIC a runtime setting rather than a compile time one, so we can drop more NVIC ifdefs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-19hw/arm_gic: Make CPU target registers RAZ/WI on uniprocessorPeter Maydell1-23/+33
The GIC spec says that the CPU target registers should RAZ/WI for uniprocessor implementations. Implement this, which also conveniently lets us drop an NVIC ifdef. Annoyingly, the 11MPCore's GIC is the odd one out, since it always has these registers, even in uniprocessor configs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-19hw/arm_gic: Add qdev property for GIC revisionPeter Maydell1-0/+10
GIC behaviour can be different between revision 1 and 2 of the architectural GIC specification; we also have to handle the legacy 11MPCore GIC, which is different again in some places. Introduce a qdev property so we can behave appropriately. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-19hw/armv7m_nvic: Use MemoryRegions for NVIC specific registersPeter Maydell1-27/+6
Implement the NVIC specific register areas using a set of overlaid MemoryRegions in a container, rather than by having the arm_gic read/write functions use special purpose callbacks. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-19hw/arm_gic: Move NVIC specific reset to armv7m_nvic_resetPeter Maydell1-10/+0
Move the NVIC specific bits of reset to the NVIC's own reset function, rather than using ifdefs in the common arm_gic reset. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-19hw/arm_gic: Remove the special casing of NCPU for the NVICPeter Maydell1-20/+3
Drop the special casing of NCPU=1 for the NVIC. This slightly increases the amount of memory used by its state structure, but removes some ifdeffery and means we can safely move the GIC state into a common subclass structure. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-19hw/arm_gic: Remove NVIC ifdefs from gic_state structPeter Maydell1-12/+3
Remove some NVIC ifdefs from the gic_state struct and its state save/load functions. This means there are some fields in it which are present for the NVIC but not used, but means it always has the same layout and can be pulled out into a common subclass. Note that the addition of irq_target[] to the save/load struct for the NVIC requires a vmstate version bump. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de>
2012-04-13hw/arm_gic: Remove stray hardcoded tabPeter Maydell1-1/+1
Remove the single instance of a hardcoded tab from hw/arm_gic.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13hw/arm_gic: gic_set_pending_private() is NVIC onlyPeter Maydell1-2/+3
The function gic_set_pending_private() is now used by the NVIC only (for the GIC we now set PPI interrupts via gpio lines and gic_set_irq()). So make it #ifdef NVIC and remove the 'attribute unused' annotation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13hw/arm_gic: Use NVIC instead of LEGACY_INCLUDED_GIC definePeter Maydell1-3/+10
Now all the A profile cores have been switched to use the standalone sysbus GIC, the only remaining code which #includes arm_gic.c is the v7M NVIC. The coupling is much closer here so it's not so easily disentangled. For now, add a comment about how arm_gic.c is compiled, and assume that the NVIC always includes arm_gic.c and the non-NVIC GIC is always compiled standalone. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13hw/arm_gic: Make gic_reset a sysbus reset functionPeter Maydell1-2/+3
Make gic_reset a sysbus reset function, so we actually reset the GIC on system reset rather than only at init. For the NVIC this requires us also to implement reset of the SysTick. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13hw/arm_gic: Make the GIC its own sysbus devicePeter Maydell1-1/+51
Compile arm_gic.c as a standalone C file to produce a self contained sysbus GIC device. Support the legacy usage by #include of the .c file by making those users #define LEGACY_INCLUDED_GIC, so we can convert them one by one. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Evgeny Voevodin <e.voevodin@samsung.com>
2012-04-13hw/arm_gic: Expose PPI inputs as gpio inputsPeter Maydell1-9/+40
Expose the Private Peripheral Interrupt inputs as GPIO inputs. The layout of the GPIO array is thus: [0..N-1] SPIs [N..N+31] PPIs for CPU 0 [N+32..N+63] PPIs for CPU 1 ... Treating PPIs as being another kind of input line is in line with the GIC architecture specification, where they are clearly described that way. The 11MPCore TRM is a bit more ambiguous, but there is no practical difference between "set PPI X as pending" and "0->1 transition on a PPI input line configured as edge triggered", and PPIs are always edge triggered, so this change won't affect behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-13hw/arm_gic: Move gic_get_current_cpu into arm_gic.cPeter Maydell1-5/+15
Move the gic_get_current_cpu() function into arm_gic.c. There are only two implementations: (1) "get the index of the currently executing CPU", used by all multicore GICs, and (2) "always 0", used by all GICs instantiated with a single CPU interface (the Realview board GIC and the v7M NVIC). So we can move this into the main GIC source file. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Evgeny Voevodin <e.voevodin@samsung.com>
2012-04-13hw/arm_gic: Move NCPU definition to arm_gic.cPeter Maydell1-1/+12
Move the NCPU definition to arm_gic.c: the maximum number of CPU interfaces is defined by the GIC architecture specification to be 8, so we don't need to have this #define in each of the sources files which currently includes arm_gic.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Evgeny Voevodin <e.voevodin@samsung.com>
2012-03-16ARM: Remove unnecessary subpage workaroundsPeter Maydell1-4/+4
In the ARM per-CPU peripherals (GIC, private timers, SCU, etc), remove workarounds for subpage memory region read/write functions being passed offsets from the start of the page rather than the start of the region. Following commit 5312bd8b3 the masking off of high bits of the address offset is now harmless but unnecessary. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de>
2012-03-02arm: make sure that number of irqs can be represented in GICD_TYPER.Rusty Russell1-0/+9
We currently assume that the number of interrupts (ITLinesNumber in the architecture reference manual) is divisible by 32, since we present it to the guest when it reads GICD_TYPER (in gic_dist_readb()) as (N / 32) - 1. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-03-02arm: clean up GIC constantsRusty Russell1-19/+22
Interrupts numbers 0-31 are private to the processor interface, 32-1019 are general interrupts. Add GIC_INTERNAL and substitute everywhere. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> [Peter Maydell: converted some tabs to spaces] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-17arm: make the number of GIC interrupts configurableMark Langsdorf1-30/+38
Increase the maximum number of GIC interrupts for a9mp and a11mp to 1020, and create a configurable property for each defaulting to 96 and 64 (respectively) so that device modelers can set the value appropriately for their SoC. Other ARM processors also set their maximum number of used IRQs appropriately. Set the maximum theoretical number of GIC interrupts to 1020 and update the save/restore code to only use the appropriate number for each SoC. Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Reviewed-by: Andreas Färber <afaerber@suse.de> [Peter Maydell: fixed minor whitespace snafu] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-04arm: add dummy gic security registersRob Herring1-0/+6
Implement handling for the RAZ/WI gic security registers. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-14Merge remote-tracking branch 'stefanha/trivial-patches-next' into stagingAnthony Liguori1-1/+1
2011-12-12hw/arm_gic: Expose GIC CPU interfaces as sysbus memory regionsPeter Maydell1-1/+74
Expose the ARM GIC CPU interfaces as memory regions, rather than just providing read and write functions for them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-06fix spelling in hw sub directoryDong Xu Wang1-1/+1
Correct obvious spelling errors in qemu/hw directory. Signed-off-by: Dong Xu Wang <wdongxu@linux.vnet.ibm.com> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-12-05hw/arm_gic.c: Ignore attempts to complete nonexistent IRQsPeter Maydell1-9/+18
Ignore attempts to complete non-existent IRQs; this fixes a buffer overrun if the guest writes a bad value to the GICC_EOIR register. (This case is UNPREDICTABLE so ignoring it is a valid choice.) Note that doing nothing if the guest writes 1023 to this register is not in fact a change in behaviour: the old code would also always do nothing in this case but in a non-obvious way. (The buffer overrun was noted by Coverity, see bug 887883.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2011-11-06arm_gic: handle banked enable bits for per-cpu interruptsRabin Vincent1-15/+20
The first enable set/clear register (which controls the PPIs and SGIs) is supposed to be banked for each processor. Currently it is just handled globally and this prevents recent SMP Linux kernels from booting, because CPU0 stops receiving localtimer interrupts when CPU1 disables them locally. To fix this, allow the enable bits to be enabled per-cpu. For SPIs, always enable/disable ALL_CPU_MASK. Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-10-21hw/arm_gic.c: Fix save/load of irq_target arrayDmitry Koshelev1-8/+8
irq_target array saving/loading is in the wrong loop. Version bump. Signed-off-by: Dmitry Koshelev <karaghiozis@gmail.com> Acked-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2011-08-22arm_gic: convert to memory APIAvi Kivity1-14/+8
Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-07-23Correct spelling of licensedMatthew Fernandez1-1/+1
Correct typos of "licenced" to "licensed". Reviewed-by: Stefan Weil <weil@mail.berlios.de> Reviewed-by: Andreas F=E4rber <andreas.faerber@web.de> Signed-off-by: Matthew Fernandez <matthew.fernandez@gmail.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-03-06target-arm: Fix soft interrupt in GIC distributorAdam Lackorzynski1-2/+2
Fix selection of target list filter mode. Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-11Add endianness as io mem parameterAlexander Graf1-1/+2
As stated before, devices can be little, big or native endian. The target endianness is not of their concern, so we need to push things down a level. This patch adds a parameter to cpu_register_io_memory that allows a device to choose its endianness. For now, all devices simply choose native endian, because that's the same behavior as before. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-06savevm: Add DeviceState paramAlex Williamson1-1/+1
When available, we'd like to be able to access the DeviceState when registering a savevm. For buses with a get_dev_path() function, this will allow us to create more unique savevm id strings. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-11-19ARM PBX-A9 board supportPaul Brook1-1/+1
Implement ARM RealView PBX-A9 board support. Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-11-13ARM MPCore tweaksPaul Brook1-6/+22
Allow the user to specify the number of cores present on the RealView EB + ARM11MPCore board. Also split into its own config rather than guessing from the CPU name. Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-10-01Revert "Get rid of _t suffix"Anthony Liguori1-6/+6
In the very least, a change like this requires discussion on the list. The naming convention is goofy and it causes a massive merge problem. Something like this _must_ be presented on the list first so people can provide input and cope with it. This reverts commit 99a0949b720a0936da2052cb9a46db04ffc6db29. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01Get rid of _t suffixmalc1-6/+6
Some not so obvious bits, slirp and Xen were left alone for the time being. Signed-off-by: malc <av1474@comtv.ru>
2009-08-25Make CPURead/WriteFunc structure 'const'Blue Swirl1-2/+2
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-06-16Remove io_index argument from cpu_register_io_memory()Avi Kivity1-1/+1
The parameter is always zero except when registering the three internal io regions (ROM, unassigned, notdirty). Remove the parameter to reduce the API's power, thus facilitating future change. Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
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