summaryrefslogtreecommitdiff
path: root/hw/block/nvme.c
AgeCommit message (Collapse)AuthorFilesLines
2013-10-14hw: set interrupts using pci irq wrappersMarcel Apfelbaum1-1/+1
pci_set_irq and the other pci irq wrappers use PCI_INTERRUPT_PIN config register to compute device INTx pin to assert/deassert. An irq is allocated using pci_allocate_irq wrapper only if is needed by non pci devices. Removed irq related fields from state if not used anymore. Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-08-22aio / timers: Switch entire codebase to the new timer APIAlex Bligh1-10/+10
This is an autogenerated patch using scripts/switch-timer-api. Switch the entire code base to using the new timer API. Note this patch may introduce some line length issues. Signed-off-by: Alex Bligh <alex@alex.org.uk> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-07-29devices: Associate devices to their logical categoryMarcel Apfelbaum1-0/+1
The category will be used to sort the devices displayed in the command line help. Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com> Message-id: 1375107465-25767-4-git-send-email-marcel.a@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-04hw/block: pass owner to memory_region_init* functionsPaolo Bonzini1-1/+2
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-07-04memory: add owner argument to initialization functionsPaolo Bonzini1-1/+1
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-06-20dma: eliminate DMAContextPaolo Bonzini1-1/+1
The DMAContext is a simple pointer to an AddressSpace that is now always already available. Make everyone hold the address space directly, and clean up the DMA API to use the AddressSpace directly. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-06-17NVMe: Initial commit for new storage interfaceKeith Busch1-0/+885
Initial commit for emulated Non-Volatile-Memory Express (NVMe) pci storage device. NVMe is an open, industry driven storage specification defining an optimized register and command set designed to deliver the full capabilities of non-volatile memory on PCIe SSDs. Further information may be found on the organizations website at: http://www.nvmexpress.org/ This commit implements the minimum from the specification to work with existing drivers. Cc: Keith Busch <keith.busch@gmail.com> Signed-off-by: Keith Busch <keith.busch@intel.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
generated by cgit v1.2.1 (git 2.18.0) at 2024-05-14 16:34:24 +0000