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2017-12-18hw: use "qemu/osdep.h" as first #include in source filesPhilippe Mathieu-Daudé1-0/+1
applied using ./scripts/clean-includes Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2017-08-02cpu: don't allow negative core idLaurent Vivier1-0/+5
With pseries machine type a negative core-id is not managed properly: -1 gives an inaccurate error message ("core -1 already populated"), -2 crashes QEMU (core dump) As it seems a negative value is invalid for any architecture, instead of checking this in spapr_core_pre_plug() I think it's better to check this in the generic part, core_prop_set_core_id() Signed-off-by: Laurent Vivier <lvivier@redhat.com> Message-Id: <20170802103259.25940-1-lvivier@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-06-09hw/cpu: core.c can be compiled as common objectThomas Huth1-2/+1
There does not seem to be any target specific code in core.c, so we can put it into "common-obj" instead of "obj" to compile it only once for all targets. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-27Introduce DEVICE_CATEGORY_CPU for CPU devicesThomas Huth1-0/+8
Now that CPUs show up in the help text of "-device ?", we should group them into an appropriate category. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <1484917276-7107-1-git-send-email-thuth@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-17cpu: Abstract CPU core typeBharata B Rao2-0/+89
Add an abstract CPU core type that could be used by machines that want to define and hotplug CPUs in core granularity. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Igor Mammedov <imammedo@redhat.com> [Integer core property] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Igor Mammedov <imammedo@redhat.com> [dwg: changed property names to 'core-id' and 'nr-threads'] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-05-19explicitly include qom/cpu.hPaolo Bonzini1-0/+1
exec/cpu-all.h includes qom/cpu.h. Explicit inclusion will keep things working when cpu.h will not be included indirectly almost everywhere (either directly or through qemu-common.h). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-22include/qemu/osdep.h: Don't include qapi/error.hMarkus Armbruster4-0/+4
Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the Error typedef. Since then, we've moved to include qemu/osdep.h everywhere. Its file comment explains: "To avoid getting into possible circular include dependencies, this file should not include any other QEMU headers, with the exceptions of config-host.h, compiler.h, os-posix.h and os-win32.h, all of which are doing a similar job to this file and are under similar constraints." qapi/error.h doesn't do a similar job, and it doesn't adhere to similar constraints: it includes qapi-types.h. That's in excess of 100KiB of crap most .c files don't actually need. Add the typedef to qemu/typedefs.h, and include that instead of qapi/error.h. Include qapi/error.h in .c files that need it and don't get it now. Include qapi-types.h in qom/object.h for uint16List. Update scripts/clean-includes accordingly. Update it further to match reality: replace config.h by config-target.h, add sysemu/os-posix.h, sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h comment quoted above similarly. This reduces the number of objects depending on qapi/error.h from "all of them" to less than a third. Unfortunately, the number depending on qapi-types.h shrinks only a little. More work is needed for that one. Signed-off-by: Markus Armbruster <armbru@redhat.com> [Fix compilation without the spice devel packages. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-04hw/intc/arm_gic.c: Implement GICv2 GICC_DIRPeter Maydell1-1/+1
The GICv2 introduces a new CPU interface register GICC_DIR, which allows an OS to split the "priority drop" and "deactivate interrupt" parts of interrupt completion. Implement this register. (Note that the register is at offset 0x1000 in the CPU interface, which means it is on a different 4K page from all the other registers.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1456854176-7813-1-git-send-email-peter.maydell@linaro.org
2016-01-29hw: Clean up includesPeter Maydell1-0/+1
Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1453832250-766-38-git-send-email-peter.maydell@linaro.org
2016-01-29arm devices: Clean up includesPeter Maydell3-0/+3
Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1453832250-766-36-git-send-email-peter.maydell@linaro.org
2015-10-02icc_bus: drop the unused filesZhu Guihua2-119/+0
ICC bus impl has been droped, so all icc related files are not useful any more; delete them. Signed-off-by: Zhu Guihua <zhugh.fnst@cn.fujitsu.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-09-14hw/cpu/{a15mpcore, a9mpcore}: Handle missing has_el3 CPU props gracefullyEdgar E. Iglesias2-2/+2
Handle missing CPU support for EL3 gracefully. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1442135278-25281-2-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-08hw/cpu/{a15mpcore, a9mpcore}: enable TrustZone in GIC if it is enabled in CPUsPeter Maydell2-0/+24
If the A9 and A15 CPUs which we're creating the peripherals for have TrustZone (EL3) enabled, then also enable it in the GIC we create. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1441383782-24378-5-git-send-email-peter.maydell@linaro.org
2015-08-13hw/cpu/a15mpcore: Wire up hyp and secure physical timer interruptsPeter Maydell1-7/+14
Since we now support both the hypervisor and the secure physical timer, wire their interrupt lines up in the a15mpcore wrapper object. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1437047249-2357-5-git-send-email-peter.maydell@linaro.org Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-08-13Introduce gic_class_name() instead of repeating conditionPavel Fedin1-6/+2
This small inline returns correct GIC class name depending on whether we use KVM acceleration or not. Avoids duplicating the condition everywhere. Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 4f26901be9b844b563673ce3ad08eeedbb7a7132.1438758065.git.p.fedin@samsung.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-11-03icc_bus: fix typo ICC_BRIGDE -> ICC_BRIDGEZhu Guihua1-2/+2
Rename ICC_BRIGDE for better readability. Signed-off-by: Zhu Guihua <zhugh.fnst@cn.fujitsu.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-10-15target-i386: ICC bus: Drop BusState::allow_hotplugIgor Mammedov1-8/+0
Since bus_add_child() no longer cares if BUS is hotpluggable or not, there is no need in setting allow_hotplug field. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-12-24icc_bus: QOM'ify ICCxiaoqiang zhao1-8/+6
For consistency, QOM'ify APIC's parent bus. Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-12-10cpu/a9mpcore: Add Global TimerFrançois LEGAL1-5/+21
Add the global timer to A9 MPCore. Signed-off-by: François LEGAL <devel@thom.fr.eu.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: ff92f35f438ac671b57d99d823723dd3e62d2c49.1385969450.git.peter.crosthwaite@xilinx.com [PC Changes: * new commit message * split off original version as a separate patch * Rebased against new mpcore implementation (with struct embedding) ] Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10cpu/a9mpcore: reorder operations/declarationsPeter Crosthwaite1-14/+14
To make it consistent for easier code reading. The order in which variables are defined and functions are called is set to match the address map ordering. The new consistent order of doing stuff is: SCU -> GIC -> MPTimer -> WDT. 0 functional change. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 8f31398e6d9a93f57291399f269039da1a77a2b5.1385969450.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10cpu/a9mpcore: rename timerbusdev variablePeter Crosthwaite1-4/+4
Rename this variable for consistency with the above defined mptimerdev variable. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 28939ef95589a62414634e86c47cef76b21b15f7.1385969450.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-11-05arm11mpcore: Split off RealView MPCoreAndreas Färber3-121/+140
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-11-05arm11mpcore: Prepare for QOM embeddingAndreas Färber1-26/+1
Move state struct, type constant and cast macro to a new header. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-11-05arm11mpcore: Convert mpcore_rirq_state to QOM realizeAndreas Färber1-14/+44
Embed ARM11MPCorePriveState and RealViewGICState and replace SysBus initfn with realizefn. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-11-05arm11mpcore: Convert ARM11MPCorePriveState to QOM realizeAndreas Färber1-28/+56
Embed child devices and replace SysBus initfn with realizefn. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-11-05arm11mpcore: Split off SCU deviceAndreas Färber1-51/+14
Inspired by a9scu. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-11-05arm11mpcore: Create container MemoryRegion in instance_initAndreas Färber1-3/+11
This allows to map the region directly after object initialization. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-11-05arm11mpcore: Drop unused fieldsAndreas Färber1-2/+0
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-11-05arm11mpcore: Fix typo in MemoryRegion nameAndreas Färber1-1/+1
"mpcode" -> "mpcore" Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-11-05a15mpcore: Prepare for QOM embeddingAndreas Färber1-20/+1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <andreas.faerber@web.de>
2013-11-05a15mpcore: Convert to QOM realizeAndreas Färber1-8/+12
Turn SysBusDevice initfn into a QOM realizefn. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <andreas.faerber@web.de>
2013-11-05a15mpcore: Embed GICStateAndreas Färber1-15/+24
This covers both emulated and KVM GIC. Prepares for QOM realize. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <andreas.faerber@web.de>
2013-11-05a15mpcore: Split off instance_initAndreas Färber1-3/+10
Prepares for QOM realize. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <andreas.faerber@web.de>
2013-11-05a9mpcore: Prepare for QOM embeddingAndreas Färber1-23/+1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <andreas.faerber@web.de>
2013-11-05a9mpcore: Convert to QOM realizeAndreas Färber1-10/+26
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <andreas.faerber@web.de>
2013-11-05a9mpcore: Embed ARMMPTimerStateAndreas Färber1-11/+18
Prepares for QOM realize. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <andreas.faerber@web.de>
2013-11-05a9mpcore: Embed A9SCUStateAndreas Färber1-6/+10
Prepares for QOM realize. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <andreas.faerber@web.de>
2013-11-05a9mpcore: Embed GICStateAndreas Färber1-9/+16
Prepares for conversion to QOM realize. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <andreas.faerber@web.de>
2013-11-05a9mpcore: Split off instance_initAndreas Färber1-3/+9
Prepares for QOM realize. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <andreas.faerber@web.de>
2013-09-03Merge remote-tracking branch 'afaerber/tags/qom-cpu-for-anthony' into stagingAnthony Liguori1-3/+2
QOM CPUState refactorings / X86CPU * Conversion of global CPU list to QTAILQ - preparing for CPU hot-unplug * Document X86CPU magic numbers for CPUID cache info # gpg: Signature made Tue 03 Sep 2013 10:59:22 AM CDT using RSA key ID 3E7E013F # gpg: Can't check signature: public key not found # By Andreas Färber (3) and Eduardo Habkost (1) # Via Andreas Färber * afaerber/tags/qom-cpu-for-anthony: target-i386: Use #defines instead of magic numbers for CPUID cache info cpu: Replace qemu_for_each_cpu() cpu: Use QTAILQ for CPU list a15mpcore: Use qemu_get_cpu() for generic timers
2013-09-03a15mpcore: Use qemu_get_cpu() for generic timersAndreas Färber1-3/+2
This simplifies the loop and aids with refactoring of CPU list. Requested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-08-30qdev: Pass size to qbus_create_inplace()Andreas Färber1-1/+2
To be passed to object_initialize(). Since commit 39355c3826f5d9a2eb1ce3dc9b4cdd68893769d6 the argument is void*, so drop some superfluous (BusState *) casts or direct parent field usages. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-08-20default-configs: Fix A9MP and A15MP config namesPeter Maydell1-2/+2
When individual CONFIG_ switches for the A9MPcore and A15MPcore devices were created, they were inadvertently given incorrect names (CONFIG_ARM9MPCORE and CONFIG_ARM15MPCORE). These CPUs are "Cortex-A9MP" and "Cortex-A15MP", and in particular the ARM9 is a different (rather older) CPU than the Cortex-A9. Rename the CONFIG_ switches to bring them into line with the source file names and CPU names. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1376056215-26391-1-git-send-email-peter.maydell@linaro.org
2013-08-20hw/cpu/a15mpcore: Wire generic timer outputs to GIC inputsPeter Maydell1-0/+18
Now our A15 CPU implements the generic timers, we can wire them up to the appropriate inputs on the GIC. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 1376065080-26661-5-git-send-email-peter.maydell@linaro.org
2013-07-29arm11mpcore: QOM cast cleanups for mpcore_rirq_stateAndreas Färber1-7/+13
Introduce a type constant, use QOM casts, rename the parent field and prepare for QOM realize. Reviewed-by: Hu Tao <hutao@cn.fujitsu.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29arm11mpcore: QOM cast cleanups for ARM11MPCorePriveStateAndreas Färber1-8/+14
Introduce a type constant, use QOM casts and rename the parent field. Reviewed-by: Hu Tao <hutao@cn.fujitsu.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29cpu/a15mpcore: QOM cast cleanupAndreas Färber1-4/+11
Introduce type constant and cast macro and rename A15MPPrivState::busdev field to parent_obj to enforce its use. Prepares for QOM realize. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <andreas.faerber@web.de>
2013-07-29cpu/a9mpcore: QOM casting cleanupAndreas Färber1-4/+11
Introduce type constant and cast macro and enforce its use by renaming A9MPPrivState::busdev field to parent_obj. Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <andreas.faerber@web.de>
2013-07-29devices: Associate devices to their logical categoryMarcel Apfelbaum1-0/+8
The category will be used to sort the devices displayed in the command line help. Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com> Message-id: 1375107465-25767-4-git-send-email-marcel.a@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-15hw/cpu/a15mpcore: Correct default value for num-irqPeter Maydell1-2/+2
The a15mpcore device claims that its default value for num-irq is the number of interrupts used by the A15MP in the vexpress-a15 board. However that chip has 128 external interrupts, not 64. Since there is only one A15 based model in QEMU currently, we can fix this by simply changing the default value. This error was causing recent (3.10) Linux kernels to print warnings/backtraces when the number of interrupts reported by the GIC was smaller than an interrupt number they wanted to use. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1373032481-15280-1-git-send-email-peter.maydell@linaro.org
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