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2013-09-02xics: move registration of global state to realize()Alexey Kardashevskiy1-10/+11
Registration of global state belongs into realize so move it there. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-08-30qom: Pass available size to object_initialize()Andreas Färber1-1/+1
To be passed on to object_initialize_with_type(). Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> (virtio-ccw) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-08-22aio / timers: Switch entire codebase to the new timer APIAlex Bligh4-19/+19
This is an autogenerated patch using scripts/switch-timer-api. Switch the entire code base to using the new timer API. Note this patch may introduce some line length issues. Signed-off-by: Alex Bligh <alex@alex.org.uk> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-07-29ioapic: QOM cast cleanupAndreas Färber1-1/+1
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29xilinx_intc: QOM cast cleanupAndreas Färber1-7/+12
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29slavio_intctl: QOM cast cleanupAndreas Färber1-17/+18
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29realview_gic: QOM cast cleanupAndreas Färber1-7/+13
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29puv3_intc: QOM cast cleanupAndreas Färber1-9/+14
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29pl190: QOM cast cleanupAndreas Färber1-18/+22
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29pl190: Rename pl190_state to PL190StateAndreas Färber1-21/+21
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29omap_intc: QOM'ify omap-intc and omap2-intcAndreas Färber1-22/+35
Create a new abstract base type and let omap-intc and omap2-intc inherit from it. Introduce a type constant and use QOM casts. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29lm32_pic: QOM cast cleanupAndreas Färber1-11/+16
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29grlib_irqmp: QOM cast cleanupAndreas Färber1-23/+10
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29exynos4210_gic: QOM cast cleanup for exynos4210.irq_gateAndreas Färber1-9/+14
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29exynos4210_gic: QOM cast cleanup for exynos4210.gicAndreas Färber1-8/+14
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29exynos4210_combiner: QOM cast cleanupAndreas Färber1-9/+14
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29etraxfs_pic: QOM cast cleanupAndreas Färber1-8/+14
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29arm_gic: QOM cast cleanupAndreas Färber3-4/+8
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29imx_avic: QOM cast cleanupAndreas Färber1-10/+17
Introduce type constant, use QOM casts and prepare SysBus initfn for QOM realize by resolving SysBusDevice vs. DeviceState "dev" name conflict. Acked-by: Peter Chubb <peter.chubb@nicta.com.au> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-29xics: rename types to be sane and follow coding styleAnthony Liguori1-112/+233
Basically, in HW the layout of the interrupt network is: - One ICP per processor thread (the "presenter"). This contains the registers to fetch a pending interrupt (ack), EOI, and control the processor priority. - One ICS per logical source of interrupts (ie, one per PCI host bridge, and a few others here or there). This contains the per-interrupt source configuration (target processor(s), priority, mask) and the per-interrupt internal state. Under PAPR, there is a single "virtual" ICS ... somewhat (it's a bit oddball what pHyp does here, arguably there are two but we can ignore that distinction). There is no register level access. A pair of firmware (RTAS) calls is used to configure each virtual interrupt. So our model here is somewhat the same. We have one ICS in the emulated XICS which arguably *is* the emulated XICS, there's no point making it a separate "device", that would just be gross, and each VCPU has an associated ICP. Yet we call the "XICS" struct icp_state and then the ICPs 'struct icp_server_state'. It's particularly confusing when all of the functions have xics_prefixes yet take *icp arguments. Rename: struct icp_state -> XICSState struct icp_server_state -> ICPState struct ics_state -> ICSState struct ics_irq_state -> ICSIRQState Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Message-id: 1374175984-8930-12-git-send-email-aliguori@us.ibm.com [aik: added ics_resend() on post_load] Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-23ioapic: Use QOM realize for ioapicHu Tao1-7/+5
Signed-off-by: Hu Tao <hutao@cn.fujitsu.com> [AF: Tweaked error message] Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-11pseries: move interrupt controllers to hw/intc/Alexey Kardashevskiy2-0/+588
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-09intc/openpic: Build openpic only onceAndreas Färber2-2/+2
Since current_cpu is CPUState it no longer depends on CPUPPCState. Move ppce500_set_mpic_proxy() to a new hw/ppc/ppc_e500.h because hw/ppc/ppc.h is too heavily using CPUPPCState and PowerPCCPU. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-09intc/arm_gic: Build arm_gic only onceAndreas Färber2-1/+2
Since current_cpu is CPUState it no longer needs CPUArchState. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-09cpu: Make first_cpu and next_cpu CPUStateAndreas Färber1-3/+2
Move next_cpu from CPU_COMMON to CPUState. Move first_cpu variable to qom/cpu.h. gdbstub needs to use CPUState::env_ptr for now. cpu_copy() no longer needs to save and restore cpu_next. Acked-by: Paolo Bonzini <pbonzini@redhat.com> [AF: Rebased, simplified cpu_copy()] Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-09cpu: Replace cpu_single_env with CPUState current_cpuAndreas Färber3-10/+11
Move it to qom/cpu.h. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-04hw/i*: pass owner to memory_region_init* functionsPaolo Bonzini19-33/+45
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-07-04memory: add owner argument to initialization functionsPaolo Bonzini21-35/+35
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-07-01intc/openpic_kvm: Fix QOM and build issuesAndreas Färber1-21/+33
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01intc/openpic: Convert to QOM realizeAndreas Färber1-15/+19
Split qdev initfn into instance_init and realize functions. Change one occurrence of "klass" while at it. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01intc/openpic: QOM'ifyAndreas Färber1-6/+11
Introduce type constant and cast macro. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01kvm/openpic: in-kernel mpic supportScott Wood2-0/+253
Enables support for the in-kernel MPIC that thas been merged into the KVM next branch. This includes irqfd/KVM_IRQ_LINE support from Alex Graf (along with some other improvements). Note from Alex regarding kvm_irqchip_create(): On x86, one would call kvm_irqchip_create() to initialize an in-kernel interrupt controller. That function then goes ahead and initializes global capability variables as well as the default irq routing table. On ppc, we can't call kvm_irqchip_create() because we can have different types of interrupt controllers. So we want to do all the things that function would do for us in the in-kernel device init handler. Signed-off-by: Scott Wood <scottwood@freescale.com> [agraf: squash in kvm_irqchip_commit_routes patch, fix non-kvm build, fix ppcemb] Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-01openpic: factor out some common defines into openpic.hScott Wood1-22/+18
...for use by the KVM in-kernel irqchip stub. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-06-18intc/xilinx_intc: Dont lower IRQ when HIE clearedPeter Crosthwaite1-5/+0
This is a little strange. It is lowering the parent IRQ pin on input when HIE is cleared. There is no such behaviour in the real hardware. ISR changes based on interrupt pin state are already guarded on HIE being set. So we can just delete this if in its entirety. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2013-06-18intc/xilinx_intc: Inhibit write to ISR when HIEPeter Crosthwaite1-0/+5
When the Hardware Interrupt Enable (HIE) bit is set, software cannot change ISR. Add write guard accordingly. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2013-06-18intc/xilinx_intc: Handle level interrupt retriggeringPeter Crosthwaite1-1/+15
Acking a level sensitive interrupt should have no effect if the interrupt pin is still asserted. The current implementation requires and edge condition to occur for setting a level sensitive IRQ, which means an ACK can clear a level sensitive interrupt, until the original source strobes the interrupt again. Fix by keeping track of the interrupt pin state and setting ISR based on this every time update_irq() is called. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2013-06-18intc/xilinx_intc: Don't clear level sens. IRQs without ACKPeter Crosthwaite1-7/+1
For level sensitive interrupts, ISR bits are cleared when the input pin is lowered. This is incorrect. Only software can clear ISR bits (via IAR or direct write to ISR with !MER(2)). Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2013-06-15Merge branch 'realize-isa.v2' of git://github.com/afaerber/qemu-cpuBlue Swirl2-32/+50
* 'realize-isa.v2' of git://github.com/afaerber/qemu-cpu: qdev: Drop FROM_QBUS() macro isa: QOM'ify ISADevice isa: QOM'ify ISABus i8259: Convert PICCommonState to use QOM realizefn kvm/i8259: QOM'ify some more i8259: QOM'ify some more i8254: Convert PITCommonState to QOM realizefn kvm/i8254: QOM'ify some more i8254: QOM'ify some more isa: Use realizefn for ISADevice cs4231a: QOM'ify some more gus: QOM'ify some more
2013-06-11intc/xilinx_intc: Use qemu_set_irqPeter Crosthwaite1-5/+1
Use qemu_set_irq rather than if-elsing qemu_irq_(lower|raise). No functional change, just reduces verbosity. Cc: qemu-trivial@nongnu.org Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-06-07isa: QOM'ify ISADeviceAndreas Färber1-10/+12
Rename its parent field and use DEVICE() where necessary. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-06-07i8259: Convert PICCommonState to use QOM realizefnAndreas Färber2-7/+21
Instead of having the parent provide PICCommonClass::init, let the children override DeviceClass::realize themselves. This pushes the responsibility of saving and calling the parent's realizefn to the children. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-06-07i8259: QOM'ify some moreAndreas Färber1-9/+14
Introduce type constant. Prepares for PIC realizefn. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-06-07isa: Use realizefn for ISADeviceAndreas Färber1-6/+3
Drop ISADeviceClass::init and the resulting no-op initfn and let children implement their own realizefn. Adapt error handling. Split off an instance_init where sensible. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-06-02apic: rename apic specific bitoptsMichael S. Tsirkin1-21/+21
apic has its own version of bitops, with the difference that it works on u32 and not long. Add apic_ prefix to avoid namespace clashes. We should look into reusing standard bitops long-term, but that's not entirely trivial. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-05-26Remove Sun4c, Sun4d and a few CPUsBlue Swirl3-365/+1
Sun4c and Sun4d architectures and related CPUs are not fully implemented (especially Sun4c MMU) and there has been no interest for them. Likewise, a few CPUs (Cypress, Ross etc) are only half implemented. Remove the machines and CPUs, they can be re-added if needed later. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-05-12remove double semicolonsDong Xu Wang1-1/+1
Signed-off-by: Dong Xu Wang <wdongxu@linux.vnet.ibm.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-05-01target-i386: Move APIC to ICC busIgor Mammedov1-6/+12
It allows APIC to be hotplugged. * map APIC's mmio at board level if it is present * do not register mmio region for each APIC, since only one is used/mapped Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-05-01target-i386: Replace MSI_SPACE_SIZE with APIC_SPACE_SIZEIgor Mammedov1-1/+1
Put APIC_SPACE_SIZE in a public header so that it can be reused elsewhere later. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-04-29i8259: QOM cleanupsAndreas Färber2-11/+13
Eliminate DO_UPCAST() for PICCommonState. Prepares for ISA realizefn. Also give the i8259_common type registration functions unique names while at it. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Message-id: 1367093935-29091-6-git-send-email-afaerber@suse.de Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-04-16ioapic: Replace FROM_SYSBUS() with QOM type castIgor Mammedov1-1/+1
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
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