summaryrefslogtreecommitdiff
path: root/hw/intc
AgeCommit message (Collapse)AuthorFilesLines
2015-06-22qerror: Clean up QERR_ macros to expand into a single stringMarkus Armbruster1-3/+3
These macros expand into error class enumeration constant, comma, string. Unclean. Has been that way since commit 13f59ae. The error class is always ERROR_CLASS_GENERIC_ERROR since the previous commit. Clean up as follows: * Prepend every use of a QERR_ macro by ERROR_CLASS_GENERIC_ERROR, and delete it from the QERR_ macro. No change after preprocessing. * Rewrite error_set(ERROR_CLASS_GENERIC_ERROR, ...) into error_setg(...). Again, no change after preprocessing. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Luiz Capitulino <lcapitulino@redhat.com>
2015-06-15arm_gic: gic_update should always update all coresJohan Karlsson1-1/+1
This patch fixes so that gic_update always updates all the cores with new pending irq states. If the function returns early it is possible to get interrupts that has already been acknowledged. Signed-off-by: Johan Karlsson <johan.karlsson@enea.com> [PMM: rebased to apply to current master] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-12migration: Use normal VMStateDescriptions for SubsectionsJuan Quintela1-6/+4
We create optional sections with this patch. But we already have optional subsections. Instead of having two mechanism that do the same, we can just generalize it. For subsections we just change: - Add a needed function to VMStateDescription - Remove VMStateSubsection (after removal of the needed function it is just a VMStateDescription) - Adjust the whole tree, moving the needed function to the corresponding VMStateDescription Signed-off-by: Juan Quintela <quintela@redhat.com>
2015-06-04Merge remote-tracking branch ↵Peter Maydell1-4/+3
'remotes/mjt/tags/pull-trivial-patches-2015-06-03' into staging trivial patches for 2015-06-03 # gpg: Signature made Wed Jun 3 14:07:47 2015 BST using RSA key ID A4C3D7DB # gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" # gpg: aka "Michael Tokarev <mjt@corpit.ru>" # gpg: aka "Michael Tokarev <mjt@debian.org>" * remotes/mjt/tags/pull-trivial-patches-2015-06-03: (30 commits) configure: postfix --extra-cflags to QEMU_CFLAGS cadence_gem: Fix Rx buffer size field mask slirp: use less predictable directory name in /tmp for smb config (CVE-2015-4037) translate-all: delete prototype for non-existent function Add -incoming help text hw/display/tc6393xb.c: Fix misusing qemu_allocate_irqs for single irq hw/arm/nseries.c: Fix misusing qemu_allocate_irqs for single irq hw/alpha/typhoon.c: Fix misusing qemu_allocate_irqs for single irq hw/unicore32/puv3.c: Fix misusing qemu_allocate_irqs for single irq hw/lm32/milkymist.c: Fix misusing qemu_allocate_irqs for single irq hw/lm32/lm32_boards.c: Fix misusing qemu_allocate_irqs for single irq hw/ppc/prep.c: Fix misusing qemu_allocate_irqs for single irq hw/sparc/sun4m.c: Fix misusing qemu_allocate_irqs for single irq hw/timer/arm_timer.c: Fix misusing qemu_allocate_irqs for single irq hw/isa/i82378.c: Fix misusing qemu_allocate_irqs for single irq hw/isa/lpc_ich9.c: Fix misusing qemu_allocate_irqs for single irq hw/i386/pc: Fix misusing qemu_allocate_irqs for single irq hw/intc/exynos4210_gic.c: Fix memory leak by adjusting order hw/arm/omap_sx1.c: Fix memory leak spotted by valgrind hw/ppc/e500.c: Fix memory leak ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-04Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into ↵Peter Maydell1-3/+6
staging X86 queue 2015-06-02 # gpg: Signature made Tue Jun 2 20:21:17 2015 BST using RSA key ID 984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-pull-request: arch_init: Drop target-x86_64.conf target-i386: Register QOM properties for feature flags apic: convert ->busdev.qdev casts to C casts target-i386: Fix signedness of MSR_IA32_APICBASE_BASE pc: Ensure non-zero CPU ref count after attaching to ICC bus Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-03hw/intc/exynos4210_gic.c: Fix memory leak by adjusting orderShannon Zhao1-4/+3
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-06-02apic: convert ->busdev.qdev casts to C castsZhu Guihua1-3/+6
Use C casts to avoid accessing ICCDevice's qdev field directly. Signed-off-by: Zhu Guihua <zhugh.fnst@cn.fujitsu.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Acked-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2015-06-02arm_gicv2m: set kvm_gsi_direct_mapping and kvm_msi_via_irqfd_allowedEric Auger1-0/+2
After introduction of kvm_arch_msi_data_to_gsi, kvm_gsi_direct_mapping now can be set on ARM. Also kvm_msi_via_irqfd_allowed can be set, depending on kernel irqfd support, hence enabling VIRTIO-PCI with vhost back-end. Signed-off-by: Eric Auger <eric.auger@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-02arm_gicv2m: Add GICv2m widget to support MSIsChristoffer Dall2-0/+191
The ARM GICv2m widget is a little device that handles MSI interrupt writes to a trigger register and ties them to a range of interrupt lines wires to the GIC. It has a few status/id registers and the interrupt wires, and that's about it. A board instantiates the device by setting the base SPI number and number SPIs for the frame. The base-spi parameter is indexed in the SPI number space only, so base-spi == 0, means IRQ number 32. When a device (the PCI host controller) writes to the trigger register, the payload is the GIC IRQ number, so we have to subtract 32 from that and then index into our frame of SPIs. When instantiating a GICv2m device, tell PCI that we have instantiated something that can deal with MSIs. We rely on the board actually wiring up the GICv2m to the PCI host controller. Reviewed-by: Eric Auger <eric.auger@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1432897270-7780-3-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-12hw/intc/arm_gic: Add grouping support to gic_update()Peter Maydell1-5/+22
Add support to gic_update() for determining the current IRQ and FIQ status when interrupt grouping is supported. This simply requires that instead of always raising IRQ we check the group of the highest priority pending interrupt and the GICC_CTLR.FIQEn bit to see whether we should raise IRQ or FIQ. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1430502643-25909-15-git-send-email-peter.maydell@linaro.org
2015-05-12hw/intc/arm_gic: Change behavior of IAR writesFabian Aggeler3-8/+18
Grouping (GICv2) and Security Extensions change the behavior of IAR reads. Acknowledging Group0 interrupts is only allowed from Secure state and acknowledging Group1 interrupts from Secure state is only allowed if AckCtl bit is set. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-14-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-14-git-send-email-greg.bellows@linaro.org [PMM: simplify significantly by reusing the existing gic_get_current_pending_irq() rather than reimplementing the same logic here] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-12hw/intc/arm_gic: Change behavior of EOIR writesFabian Aggeler3-4/+14
Grouping (GICv2) and Security Extensions change the behavior of EOIR writes. Completing Group0 interrupts is only allowed from Secure state. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-13-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-13-git-send-email-greg.bellows@linaro.org [PMM: Rather than go to great lengths to ignore the UNPREDICTABLE case of a Secure EOI of a Group1 (NS) irq with AckCtl == 0, we just let it fall through; add a comment about it.] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-12hw/intc/arm_gic: Handle grouping for GICC_HPPIRFabian Aggeler1-1/+27
Grouping (GICv2) and Security Extensions change the behaviour of reads of the highest priority pending interrupt register (ICCHPIR/GICC_HPPIR). Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-12-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-12-git-send-email-greg.bellows@linaro.org [PMM: make utility fn static; coding style fixes; AckCtl has an effect for GICv2 without security extensions as well; removed checks on enable bits because these are done when we set current_pending[cpu]] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-12hw/intc/arm_gic: Restrict priority viewFabian Aggeler3-7/+61
GICs with Security Extensions restrict the non-secure view of the interrupt priority and priority mask registers. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-11-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-15-git-send-email-greg.bellows@linaro.org [PMM: minor code tweaks; fixed missing masking in gic_set_priority_mask and gic_set_priority] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-12hw/intc/arm_gic: Implement Non-secure view of RPRFabian Aggeler1-1/+18
For GICs with Security Extensions Non-secure reads have a restricted view on the current running priority. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-10-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-11-git-send-email-greg.bellows@linaro.org [PMM: make function static, minor comment tweak] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-12hw/intc/arm_gic: Make ICCICR/GICC_CTLR bankedFabian Aggeler5-13/+72
ICCICR/GICC_CTLR is banked in GICv1 implementations with Security Extensions or in GICv2 in independent from Security Extensions. This makes it possible to enable forwarding of interrupts from the CPU interfaces to the connected processors for Group0 and Group1. We also allow to set additional bits like AckCtl and FIQEn by changing the type from bool to uint32. Since the field does not only store the enable bit anymore and since we are touching the vmstate, we use the opportunity to rename the field to cpu_ctlr. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-9-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-9-git-send-email-greg.bellows@linaro.org [PMM: rewrote to store state in a single uint32_t rather than keeping the NS and S banked variants separate; this considerably simplifies the get/set functions] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-12hw/intc/arm_gic: Make ICCBPR/GICC_BPR bankedFabian Aggeler1-5/+26
This register is banked in GICs with Security Extensions. Storing the non-secure copy of BPR in the abpr, which is an alias to the non-secure copy for secure access. ABPR itself is only accessible from secure state if the GIC implements Security Extensions. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-8-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-10-git-send-email-greg.bellows@linaro.org [PMM: rewrote to fix style issues and correct handling of GICv2 without security extensions] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-12hw/intc/arm_gic: Make ICDDCR/GICD_CTLR bankedFabian Aggeler5-14/+34
ICDDCR/GICD_CTLR is banked if the GIC has the security extensions, and the S (or only) copy has separate enable bits for Group0 and Group1 enable if the GIC implements interrupt groups. EnableGroup0 (Bit [1]) in GICv1 is architecturally IMPDEF. Since this bit (Enable Non-secure) is present in the integrated GIC of the Cortex-A9 MPCore, we support this bit in our GICv1 implementation too. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-7-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-8-git-send-email-greg.bellows@linaro.org [PMM: rewritten to store the state in a single s->ctlr uint32, with the NS register handled as an alias of bit 1 in that value; added vmstate version bump] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-12hw/intc/arm_gic_kvm.c: Save and restore GICD_IGROUPRn statePeter Maydell1-10/+20
Now that the GIC base class has state fields for the GICD_IGROUPRn registers, make kvm_arm_gic_get() and kvm_arm_gic_put() write and read them. This allows us to remove the check that made us fail migration if the guest had set any of the group register bits. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-6-git-send-email-peter.maydell@linaro.org
2015-05-12hw/intc/arm_gic: Add Interrupt Group RegistersFabian Aggeler3-5/+54
The Interrupt Group Registers allow the guest to configure interrupts into one of two groups, where Group0 are higher priority and may be routed to IRQ or FIQ, and Group1 are lower priority and always routed to IRQ. (In a GIC with the security extensions Group0 is Secure interrupts and Group 1 is NonSecure.) The GICv2 always supports interrupt grouping; the GICv1 does only if it implements the security extensions. This patch implements the ability to read and write the registers; the actual functionality the bits control will be added in a subsequent patch. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-5-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-7-git-send-email-greg.bellows@linaro.org [PMM: bring GIC_*_GROUP macros into line with the others, ie a simple SET/CLEAR/TEST rather than GROUP0/GROUP1; utility gic_has_groups() function; minor style fixes; bump vmstate version] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-12hw/intc/arm_gic: Switch to read/write callbacks with tx attributesPeter Maydell1-54/+90
Switch the GIC's MMIO callback functions to the read_with_attrs and write_with_attrs functions which provide MemTxAttrs. This will allow the GIC to correctly handle secure and nonsecure register accesses. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1430502643-25909-4-git-send-email-peter.maydell@linaro.org
2015-05-12hw/intc/arm_gic: Add Security Extensions propertyFabian Aggeler3-1/+19
Add a QOM property which allows the GIC Security Extensions to be enabled. These are an optional part of the GICv1 and GICv2 architecture. This commit just adds the property and some sanity checks that it is only enabled on GIC revisions that support it. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-3-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-5-git-send-email-greg.bellows@linaro.org [PMM: changed property name, added checks that it isn't set for older GIC revisions or if using the KVM VGIC; reworded commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-12hw/intc/arm_gic: Create outbound FIQ linesFabian Aggeler2-1/+7
Create the outbound FIQ lines from the GIC to the CPUs; these are used if the GIC has security extensions or grouping support. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-2-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-2-git-send-email-greg.bellows@linaro.org [PMM: added FIQ lines to kvm-arm-gic so its interface is the same; tweaked commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-12armv7m_nvic: systick: Reload the RELOAD value and count down only if ENABLE ↵Adrian Huang1-0/+9
bit is set Consider the following pseudo code to configure SYSTICK (The recommended programming sequence from "the definitive guide to the arm cortex-m3"): SYSTICK Reload Value Register = 0xffff SYSTICK Current Value Register = 0 SYSTICK Control and Status Register = 0x7 The pseudo code "SYSTICK Current Value Register = 0" leads to invoking systick_reload(). As a consequence, the systick.tick member is updated and the systick timer starts to count down when the ENABLE bit of SYSTICK Control and Status Register is cleared. The worst case is that: during the system initialization, the reset value of the SYSTICK Control and Status Register is 0x00000000. When the code "SYSTICK Current Value Register = 0" is executed, the systick.tick member is accumulated with "(s->systick.reload + 1) * systick_scale(s)". The systick_scale() gets the external_ref_clock scale because the CLKSOURCE bit of the SYSTICK Control and Status Register is cleared. This is the incorrect behavior because of the code "SYSTICK Control and Status Register = 0x7". Actually, we want the processor clock instead of the external reference clock. This incorrect behavior defers the generation of the first interrupt. The patch fixes the above-mentioned issue by setting the systick.tick member and modifying the systick timer only if the ENABLE bit of the SYSTICK Control and Status Register is set. In addition, the Cortex-M3 Devices Generic User Guide mentioned that "When ENABLE is set to 1, the counter loads the RELOAD value from the SYST RVR register and then counts down". This patch adheres to the statement of the user guide. Signed-off-by: Adrian Huang <adrianhuang0701@gmail.com> Reviewed-by: Jim Huang <jserv.tw@gmail.com> [PMM: minor tweak to comment text] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-04-30apic_common: improve readability of apic_reset_commonDenis V. Lunev1-4/+3
Replace call of cpu_is_bsp(s->cpu) which really returns !!(s->apicbase & MSR_IA32_APICBASE_BSP) with directly collected value. Due to this the tracepoint trace_cpu_get_apic_base((uint64_t)s->apicbase); will not be hit anymore in apic_reset_common. Signed-off-by: Denis V. Lunev <den@openvz.org> CC: Andreas Färber <afaerber@suse.de> CC: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1428414832-3104-1-git-send-email-den@openvz.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-04-30Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell1-9/+0
- miscellaneous cleanups for TCG (Emilio) and NBD (Bogdan) - next part in the thread-safe address_space_* saga: atomic access to the bounce buffer and the map_clients list, from Fam - optional support for linking with tcmalloc, also from Fam - reapplying Peter Crosthwaite's "Respect as_translate_internal length clamp" after fixing the SPARC fallout. - build system fix from Wei Liu - small acpi-build and ioport cleanup by myself # gpg: Signature made Wed Apr 29 09:34:00 2015 BST using RSA key ID 78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (22 commits) nbd/trivial: fix type cast for ioctl translate-all: use bitmap helpers for PageDesc's bitmap target-i386: disable LINT0 after reset Makefile.target: prepend $libs_softmmu to $LIBS milkymist: do not modify libs-softmmu configure: Add support for tcmalloc exec: Respect as_translate_internal length clamp ioport: reserve the whole range of an I/O port in the AddressSpace ioport: loosen assertions on emulation of 16-bit ports ioport: remove wrong comment ide: there is only one data port gus: clean up MemoryRegionPortio sb16: remove useless mixer_write_indexw sun4m: fix slavio sysctrl and led register sizes acpi-build: remove dependency from ram_addr.h memory: add memory_region_ram_resize dma-helpers: Fix race condition of continue_after_map_failure and dma_aio_cancel exec: Notify cpu_register_map_client caller if the bounce buffer is available exec: Protect map_client_list with mutex linux-user, bsd-user: Remove two calls to cpu_exec_init_all ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-04-28target-i386: disable LINT0 after resetNadav Amit1-9/+0
Due to old Seabios bug, QEMU reenable LINT0 after reset. This bug is long gone and therefore this hack is no longer needed. Since it violates the specifications, it is removed. Signed-off-by: Nadav Amit <namit@cs.technion.ac.il> Message-Id: <1428881529-29459-2-git-send-email-namit@cs.technion.ac.il> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-04-28omap_intc: convert ffs(3) to ctz32() in omap_inth_sir_update()Paolo Bonzini1-4/+5
Rewrite the loop using level &= level - 1 to clear the least significant bit after each iteration. This simplifies the loop and makes it easy to replace ffs(3) with ctz32(). Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 1427124571-28598-8-git-send-email-stefanha@redhat.com Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2015-04-28Convert ffs() != 0 callers to ctz32()Stefan Hajnoczi1-4/+4
There are a number of ffs(3) callers that do roughly: bit = ffs(val); if (bit) { do_something(bit - 1); } This pattern can be converted to ctz32() like this: zeroes = ctz32(val); if (zeroes != 32) { do_something(zeroes); } Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 1427124571-28598-6-git-send-email-stefanha@redhat.com Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2015-04-02target-i386: clear bsp bit when designating bspNadav Amit1-2/+6
Since the BSP bit is writable on real hardware, during reset all the CPUs which were not chosen to be the BSP should have their BSP bit cleared. This fix is required for KVM to work correctly when it changes the BSP bit. An additional fix is required for QEMU tcg to allow software to change the BSP bit. Signed-off-by: Nadav Amit <namit@cs.technion.ac.il> Message-Id: <1427932716-11800-1-git-send-email-namit@cs.technion.ac.il> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-04-01hw/intc: arm_gic_kvm.c restore config firstAlex Bennée1-2/+5
As there is logic to deal with the difference between edge and level triggered interrupts in the kernel we must ensure it knows the configuration of the IRQs before we restore the pending state. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-03-19Fix remaining warnings from Sparse (void return)Stefan Weil2-4/+7
Sparse report: hw/display/vga.c:2000:5: warning: returning void-valued expression hw/intc/arm_gic.c:707:9: warning: returning void-valued expression hw/intc/etraxfs_pic.c:138:9: warning: returning void-valued expression hw/nvram/fw_cfg.c:475:5: warning: returning void-valued expression hw/timer/a9gtimer.c:124:5: warning: returning void-valued expression hw/tpm/tpm_tis.c:794:5: warning: returning void-valued expression hw/usb/hcd-musb.c:558:9: warning: returning void-valued expression hw/usb/hcd-musb.c:776:13: warning: returning void-valued expression hw/usb/hcd-musb.c:867:5: warning: returning void-valued expression hw/usb/hcd-musb.c:932:5: warning: returning void-valued expression include/qom/cpu.h:584:5: warning: returning void-valued expression monitor.c:4686:13: warning: returning void-valued expression monitor.c:4690:13: warning: returning void-valued expression Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Andreas Färber <afaerber@suse.de> Cc: Luiz Capitulino <lcapitulino@redhat.com> Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-03-16Merge remote-tracking branch ↵Peter Maydell1-0/+7
'remotes/pmaydell/tags/pull-target-arm-20150316' into staging target-arm queue: * fix handling of execute-never bits in page table walks * tell kernel to initialize KVM GIC in realize function * fix handling of STM (user) with r15 in register list * ignore low bit of PC in M-profile exception return * fix linux-user get/set_tls syscalls on CPUs with TZ # gpg: Signature made Mon Mar 16 12:39:04 2015 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20150316: linux-user: Access correct register for get/set_tls syscalls on ARM TZ CPUs target-arm: Ignore low bit of PC in M-profile exception return target-arm: Fix handling of STM (user) with r15 in register list hw/intc/arm_gic: Initialize the vgic in the realize function target-arm: get_phys_addr_lpae: more xn control target-arm: fix get_phys_addr_v6/SCTLR_AFE access check target-arm: convert check_ap to ap_to_rw_prot Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-03-16hw/intc/arm_gic: Initialize the vgic in the realize functionEric Auger1-0/+7
This patch forces vgic initialization in the vgic realize function. It uses a new group/attribute that allows such operation: KVM_DEV_ARM_VGIC_GRP_CTRL/KVM_DEV_ARM_VGIC_CTRL_INIT This earlier initialization allows, for example, to setup VFIO signaling and irqfd after vgic initialization, on a reset notifier. Signed-off-by: Eric Auger <eric.auger@linaro.org> Message-id: 1426094226-8515-1-git-send-email-eric.auger@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-03-16s390x: Replace unchecked qdev_init() by qdev_init_nofail()Markus Armbruster1-5/+1
s390_flic_init() is a helper to create and realize either "s390-flic-kvm" or "s390-flic-qemu". When qdev_init() fails, it complains to stderr and succeeds. Except it can't actually fail, because the "s390-flic-qemu" is a dummy without a realize method, and "s390-flic-kvm"'s realize can't fail, even when the kernel device is really unavailable. Odd. Replace qdev_init() by qdev_init_nofail() to make "can't fail" locally obvious, and get rid of the unreachable error reporting. Cc: Christian Borntraeger <borntraeger@de.ibm.com> Cc: Cornelia Huck <cornelia.huck@de.ibm.com> Cc: Alexander Graf <agraf@suse.de> Signed-off-by: Markus Armbruster <armbru@redhat.com> Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Message-Id: <1423128889-18260-4-git-send-email-armbru@redhat.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2015-03-09openpic: convert to vmstateMark Cave-Ayland1-134/+119
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-03-09openpic: switch IRQQueue queue from inline to bitmapMark Cave-Ayland1-9/+16
This is in preparation for using VMSTATE_BITMAP in a followup vmstate migration patch. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-03-09openpic: fix up loadvm under -M mac99Mark Cave-Ayland1-5/+3
Issuing loadvm under -M mac99 would fail for two reasons: firstly an incorrect version number for openpic would cause openpic_load() to abort, and secondly a cut/paste error when restoring the IVPR and IDR registers caused subsequent vmstate sections to become misaligned and abort early. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-03-09openpic: fix segfault on -M mac99 savevmMark Cave-Ayland1-1/+1
A simple copy/paste error causes savevm on -M mac99 to segfault. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-03-09Openpic: check that cpu id is within the number of cpusFabien Chouteau1-2/+2
Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2015-02-18hmp: Name HMP info handler functions hmp_info_SUBCOMMAND()Markus Armbruster2-4/+4
Some are called do_info_SUBCOMMAND() (old ones, usually), some hmp_info_SUBCOMMAND(), some SUBCOMMAND_info(), sometimes SUBCOMMAND pointlessly differs in spelling. Normalize to hmp_info_SUBCOMMAND(), where SUBCOMMAND is exactly the subcommand name with '-' replaced by '_'. Exceptions: * sun4m_irq_info(), sun4m_pic_info() renamed to sun4m_hmp_info_irq(), sun4m_hmp_info_pic(). * lm32_irq_info(), lm32_pic_info() renamed to lm32_hmp_info_irq(), lm32_hmp_info_pic(). Signed-off-by: Markus Armbruster <armbru@redhat.com>
2015-01-26apic: do not dereference pointer before it is checked for NULLPaolo Bonzini1-3/+5
Right now you only get to apic_init_reset if you have an APIC (do_cpu_init is reached only if CPU_INTERRUPT_INIT is set and that only happens in hw/intc/apic.c). However, this is wrong because for example a port 92 or keyboard controller reset is really an INIT, and that can happen also with no APIC. So keep the check and fix the error that Coverity reported. Reported-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-01-26vmstate: accept QEMUTimer in VMSTATE_TIMER*, add VMSTATE_TIMER_PTR*Paolo Bonzini1-1/+1
Old users of VMSTATE_TIMER* are mechanically changed to VMSTATE_TIMER_PTR variants. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-12-15Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell3-2/+5
- Migration and linuxboot fixes for 2.2 regressions - valgrind/KVM support - small i386 patches - PCI SD host controller support - malloc/free cleanups from Markus (x86/scsi) - IvyBridge model - XSAVES support for KVM - initial patches from record/replay # gpg: Signature made Mon 15 Dec 2014 16:35:08 GMT using RSA key ID 78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (47 commits) sdhci: Support SDHCI devices on PCI sdhci: Define SDHCI PCI ids sdhci: Add "sysbus" to sdhci QOM types and methods sdhci: Remove class "virtual" methods sdhci: Set a default frequency clock serial: only resample THR interrupt on rising edge of IER.THRI serial: update LSR on enabling/disabling FIFOs serial: clean up THRE/TEMT handling serial: reset thri_pending on IER writes with THRI=0 linuxboot: fix loading old kernels kvm/apic: fix 2.2->2.1 migration target-i386: add Ivy Bridge CPU model target-i386: add f16c and rdrand to Haswell and Broadwell target-i386: add VME to all CPUs pc: add 2.3 machine types i386: do not cross the pages boundaries in replay mode cpus: make icount warp behave well with respect to stop/cont timer: introduce new QEMU_CLOCK_VIRTUAL_RT clock cpu-exec: invalidate nocache translation if they are interrupted icount: introduce cpu_get_icount_raw ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-15kvm/apic: fix 2.2->2.1 migrationPaolo Bonzini1-0/+5
The wait_for_sipi field is set back to 1 after an INIT, so it was not effective to reset it in kvm_apic_realize. Introduce a reset callback and reset wait_for_sipi there. Reported-by: Igor Mammedov <imammedo@redhat.com> Cc: qemu-stable@nongnu.org Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-12-15KVM_CAP_IRQFD and KVM_CAP_IRQFD_RESAMPLE checksEric Auger2-2/+0
Compute kvm_irqfds_allowed by checking the KVM_CAP_IRQFD extension. Remove direct settings in architecture specific files. Add a new kvm_resamplefds_allowed variable, initialized by checking the KVM_CAP_IRQFD_RESAMPLE extension. Add a corresponding kvm_resamplefds_enabled() function. A special notice for s390 where KVM_CAP_IRQFD was not immediatly advirtised when irqfd capability was introduced in the kernel. KVM_CAP_IRQ_ROUTING was advertised instead. This was fixed in "KVM: s390: announce irqfd capability", ebc3226202d5956a5963185222982d435378b899 whereas irqfd support was brought in 84223598778ba08041f4297fda485df83414d57e, "KVM: s390: irq routing for adapter interrupts". Both commits first appear in 3.15 so there should not be any kernel version impacted by this QEMU modification. Signed-off-by: Eric Auger <eric.auger@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-12-11arm_gic_kvm: Tell kernel about number of IRQsPeter Maydell1-0/+20
Newer kernels support a device attribute on the GIC which allows us to tell it how many IRQs this GIC instance is configured with; use it, if it exists. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1417718679-1071-1-git-send-email-peter.maydell@linaro.org
2014-11-24apic: fix incorrect handling of ExtINT interrupts wrt processor priorityPaolo Bonzini1-4/+4
This fixes another failure with ExtINT, demonstrated by QNX. The failure mode is as follows: - IPI sent to cpu 0 (bit set in APIC irr) - IPI accepted by cpu 0 (bit cleared in irr, set in isr) - IPI sent to cpu 0 (bit set in both irr and isr) - PIC interrupt sent to cpu 0 The PIC interrupt causes CPU_INTERRUPT_HARD to be set, but apic_irq_pending observes that the highest pending APIC interrupt priority (the IPI) is the same as the processor priority (since the IPI is still being handled), so apic_get_interrupt returns a spurious interrupt rather than the pending PIC interrupt. The result is an endless sequence of spurious interrupts, since nothing will clear CPU_INTERRUPT_HARD. Instead, ExtINT interrupts should have ignored the processor priority. Calling apic_check_pic early in apic_get_interrupt ensures that apic_deliver_pic_intr is called instead of delivering the spurious interrupt. apic_deliver_pic_intr then clears CPU_INTERRUPT_HARD if needed. Reported-by: Richard Bilson <rbilson@qnx.com> Tested-by: Richard Bilson <rbilson@qnx.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-11-24apic: fix loss of IPI due to masked ExtINTPaolo Bonzini1-1/+3
This patch fixes an obscure failure of the QNX kernel on QEMU x86 SMP. In QNX, all hardware interrupts come via the PIC, and are delivered by the cpu 0 LAPIC in ExtINT mode, while IPIs are delivered by the LAPIC in fixed mode. This bug happens as follows: - cpu 0 masks a particular PIC interrupt - IPI sent to cpu 0 (CPU_INTERRUPT_HARD is set) - before the IPI is accepted, the masked interrupt line is asserted by the device Since the interrupt is masked, apic_deliver_pic_intr will clear CPU_INTERRUPT_HARD. The IPI will still be set in the APIC irr, but since CPU_INTERRUPT_HARD is not set the cpu will not notice. Depending on the scenario this can cause a system hang, i.e. if cpu 0 is expected to unmask the interrupt. In order to fix this, do a full check of the APIC before an EXTINT is acknowledged. This can result in clearing CPU_INTERRUPT_HARD, but can also result in delivering the lost IPI. Reported-by: Richard Bilson <rbilson@qnx.com> Tested-by: Richard Bilson <rbilson@qnx.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-11-24apic: avoid getting out of halted state on masked PIC interruptsPaolo Bonzini1-3/+5
After the next patch, if a masked PIC interrupts causes CPU_INTERRUPT_POLL to be set, the CPU will spuriously get out of halted state. While this is technically valid, we should avoid that. Make CPU_INTERRUPT_POLL run apic_update_irq in the right thread and then look at CPU_INTERRUPT_HARD. If CPU_INTERRUPT_HARD does not get set, do not report the CPU as having work. Also move the handling of software-disabled APIC from apic_update_irq to apic_irq_pending, and always trigger CPU_INTERRUPT_POLL. This will be important once we will add a case that resets CPU_INTERRUPT_HARD from apic_update_irq. We want to run it even if we go through CPU_INTERRUPT_POLL, and even if the local APIC is software disabled. Reported-by: Richard Bilson <rbilson@qnx.com> Tested-by: Richard Bilson <rbilson@qnx.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
generated by cgit v1.2.1 (git 2.18.0) at 2024-07-08 13:51:27 +0000