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2016-03-30hw/mips: implement ITC Configuration Tags and Storage CellsLeon Alrae1-0/+1
Implement ITC as a single object consisting of two memory regions: 1) tag_io: ITC Configuration Tags (i.e. ITCAddressMap{0,1} registers) which are accessible by the CPU via CACHE instruction. Also adding MemoryRegion *itc_tag to the CPUMIPSState so that CACHE instruction will dispatch reads/writes directly. 2) storage_io: memory-mapped ITC Storage whose address space is configurable (i.e. enabled/remapped/resized) by writing to ITCAddressMap{0,1} registers. ITC Storage contains FIFO and Semaphore cells. Read-only FIFO bit in the ITC cell tag indicates the type of the cell. If the ITC Storage contains both types of cells then FIFOs are located before Semaphores. Since issuing thread can get blocked on the access to a cell (in E/F Synchronized and P/V Synchronized Views) each cell has a bitmap to track which threads are currently blocked. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips: add initial Cluster Power Controller supportLeon Alrae1-0/+1
Cluster Power Controller (CPC) is responsible for power management in multiprocessing system. It provides registers to control the power and the clock frequency of the individual elements in the system. This patch implements only three registers that are used to control the power state of each VP on a single core: * VP Run is a write-only register used to set each VP to the run state * VP Stop is a write-only register used to set each VP to the suspend state * VP Running is a read-only register indicating the run state of each VP Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips: add initial Global Config Register supportYongbok Kim1-0/+1
Add initial GCR support to indicate number of VPs present in the system, L2 bypass mode and revision number. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> [leon.alrae@imgtec.com: * removed GIC part, * changed commit message, * replaced %lx format spec. with PRIx64, * renamed mips_gcr.{c,h} to mips_cmgcr.{c,h}, * replaced CONFIG_MIPS_GIC with CONFIG_MIPS_CPS] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-16i.MX: Add i.MX6 CCM and ANALOG device.Jean-Christophe Dubois1-0/+1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Message-id: 9fa80b4d8c5d0f50c94e77d74f952a7a665e168f.1456868959.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-03bcm2835_property: add bcm2835 property channelAndrew Baumann1-0/+1
This sits behind the mailbox interface, and implements request/response queries for system properties. The framebuffer-related properties will be added in a later patch. Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-03bcm2835_mbox: add BCM2835 mailboxesAndrew Baumann1-0/+1
This adds the system mailboxes which are used to communicate with a number of GPU peripherals on Pi/Pi2. Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17hw/misc: Hyper-V test device 'hyperv-testdev'Andrey Smetanin1-0/+1
'hyperv-testdev' will be used by kvm-unit-tests to setup Hyper-V SynIC SINT's routing and to inject Hyper-V SynIC SINT's. Hyper-V test device is ISA type device that creates 0x3000 IO memory region and catches write access into it. Every write operation data decoded into ctl code and parameters for Hyper-V test device. Signed-off-by: Andrey Smetanin <asmetanin@virtuozzo.com> Reviewed-by: Roman Kagan <rkagan@virtuozzo.com> Signed-off-by: Denis V. Lunev <den@openvz.org> CC: Paolo Bonzini <pbonzini@redhat.com> CC: Richard Henderson <rth@twiddle.net> CC: Eduardo Habkost <ehabkost@redhat.com> CC: "Andreas Färber" <afaerber@suse.de> CC: Marcelo Tosatti <mtosatti@redhat.com> CC: Roman Kagan <rkagan@virtuozzo.com> CC: Denis V. Lunev <den@openvz.org> CC: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-12-17i.MX: Add an i.MX25 specific CCM class/instanceJean-Christophe Dubois1-0/+1
With this CCM, i.MX25 timer is accurate with "real world time". Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Message-id: 2c0cf90be767bfc8520661eca891ab22c61f18fe.1449528242.git.jcd@tribudubois.net Reviewed-by Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17i.MX: Split the CCM class into an abstract base class and a concrete classJean-Christophe Dubois1-0/+1
The IMX_CCM class is now the base abstract class that is used by EPIT and GPT timer implementation. IMX31_CCM class is the concrete class implementing CCM for i.MX31 SOC. For now the i.MX25 continues to use the i.MX31 CCM implementation. An i.MX25 specific CCM will be introduced in a later patch. We also rework initialization to stop using deprecated sysbus device init. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: fd3c7f87b50f5ebc99ec91f01413db35017f116d.1449528242.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-11-12hw/misc: Add support for ADC controller in Xilinx Zynq 7000Guenter Roeck1-0/+1
Add support for the Xilinx XADC core used in Zynq 7000. References: - Zynq-7000 All Programmable SoC Technical Reference Manual - 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter Tested with Linux using QEMU machine xilinx-zynq-a9 with devicetree files zynq-zc702.dtb and zynq-zc706.dtb, and kernel configuration multi_v7_defconfig. Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net> [ PC changes: * Changed macro names to match TRM where possible * Made programmers model macro scheme consistent * Dropped XADC_ZYNQ_ prefix on local macros * Fix ALM field width * Update threshold-comparison interrupts in _update_ints() * factored out DFIFO pushes into helper. Renamed to "push/pop" * Changed xadc_reg to 10 bits and added OOB check. * Reduced scope of MCTL reset to just stop channel coms. * Added dummy read data to write commands * Changed _ to - seperators in string names and filenames * Dropped ------------ in header comment * Catchall'ed _update_ints() in _write handler. * Minor whitespace changes. * Use ZYNQ_XADC_FIFO_DEPTH instead of ARRAY_SIZE() ] Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-03-11stm32f2xx_SYSCFG: Add the stm32f2xx SYSCFGAlistair Francis1-0/+1
This patch adds the stm32f2xx System Configuration Controller. This is used to configure what memory is mapped at address 0 (although that is not supported) as well as configure how the EXTI interrupts work (also not supported at the moment). This device is not required for basic examples, but more complex systems will require it (as well as the EXTI device) Signed-off-by: Alistair Francis <alistair@alistair23.me> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 5d499d7b60b61d5d6dcb310b2e55411b1f53794e.1424175342.git.alistair@alistair23.me Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-02-27Give ivshmem its own config optionDavid Gibson1-3/+1
Currently the ivshmem device is built whenever both PCI and KVM support are included. This patch gives it its own config option to allow easier customization of whether to include it. It's enabled by default in the same circumstances as now - when both PCI and KVM are available. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-Id: <1425017077-18487-4-git-send-email-david@gibson.dropbear.id.au> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-01-26hw: misc, add educational driverJiri Slaby1-0/+1
I am using qemu for teaching the Linux kernel at our university. I wrote a simple PCI device that can answer to writes/reads, generate interrupts and perform DMA. As I am dragging it locally over 2 years, I am sending it to you now. Signed-off-by: Jiri Slaby <jslaby@suse.cz> [Fix 32-bit compilation. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-12-19vfio: move hw/misc/vfio.c to hw/vfio/pci.c Move vfio.h into include/hw/vfioKim Phillips1-1/+0
This is done in preparation for the addition of VFIO platform device support. Signed-off-by: Kim Phillips <kim.phillips@linaro.org> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2014-05-24lm32: remove lm32_sysMichael Walle1-1/+0
Since we have now semihosting on the lm32 target, this device is no longer needed. Remove it. Signed-off-by: Michael Walle <michael@walle.cc>
2013-11-05pcmcia: QOM'ify PCMCIACardState and MicroDriveStateAndreas Färber1-1/+0
Turn PCMCIACardState into a device. Move callbacks to new PCMCIACardClass. Derive TYPE_MICRODRIVE from TYPE_PCMCIA_CARD. Replace ide_init2_with_non_qdev_drives(). Signed-off-by: Othmar Pasteka <pasteka@kabsi.at> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-11-05arm11mpcore: Split off SCU deviceAndreas Färber1-0/+1
Inspired by a9scu. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-11-05a9scu: Build only onceAndreas Färber1-1/+1
It does not have a target or ARMCPU dependency. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-10-31integrator: fix Linux boot failure by emulating dbg regionAlex Bennée1-0/+1
Commit 9b8c69243 (since reverted) broke the ability to boot the kernel as the value returned by unassigned_mem_read returned non-zero and left the kernel looping forever waiting for it to change (see integrator_led_set in the kernel code). Relying on a varying implementation detail is incorrect anyway so this introduces a basic stub of a memory region for the debug/LED section on the integrator board. Signed-off-by: Alex Bennée <alex@bennee.com> Message-id: 1382451366-9539-1-git-send-email-alex.bennee@linaro.org [PMM: removed three unused fields from struct IntegratorDebugState] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-04-30introduce a new qom device to deal with panicked eventHu Tao1-0/+2
pvpanic device is used to send guest panic event from guest to qemu. When guest panic happens, pvpanic device driver will write a event number to IO port 0x505(which is the IO port occupied by pvpanic device, by default). On receiving the event, pvpanic device will pause guest cpu(s), and send a qmp event QEVENT_GUEST_PANICKED. Signed-off-by: Wen Congyang <wency@cn.fujitsu.com> Signed-off-by: Hu Tao <hutao@cn.fujitsu.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Message-id: b66077a40235b3531632a05a6ff373850afc7d2e.1366945969.git.hutao@cn.fujitsu.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-04-16pci: add pci test deviceMichael S. Tsirkin1-0/+1
This device is used for kvm unit tests, currently it supports testing performance of ioeventfd. Using updated kvm unittest, here's an example output: mmio-no-eventfd:pci-mem 8796 mmio-wildcard-eventfd:pci-mem 3609 mmio-datamatch-eventfd:pci-mem 3685 portio-no-eventfd:pci-io 5287 portio-wildcard-eventfd:pci-io 1762 portio-datamatch-eventfd:pci-io 1777 Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-04-08hw: move other devices to hw/misc/, configure with default-configs/Paolo Bonzini1-0/+23
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-04-08hw: move VFIO and ivshmem to hw/misc/Paolo Bonzini1-0/+6
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-04-08hw: move target-independent files to subdirectoriesPaolo Bonzini1-0/+11
This patch tackles all files that are compiled once, moving them to subdirectories of hw/. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-04-08hw: make subdirectories for devicesPaolo Bonzini1-0/+0
Prepare the new directory structure. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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