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2012-12-14openpic: combine mpic and openpic irq raise functionsAlexander Graf2-18/+19
The IRQ raise mechanisms of the OpenPIC and MPIC controllers is identical, just that the MPIC one can also raise critical interrupts. Combine those two and check for critical raise capability during runtime. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14openpic: Convert subregions to memory apiAlexander Graf1-45/+61
The "openpic" controller is currently using one big region and does subregion dispatching manually. Move this to the memory api. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14openpic: combine mpic and openpic src handlersAlexander Graf1-47/+5
The MPIC source irq handler suddenly became identical to the standard OpenPIC source irq handler. Combine them into the same function. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14openpic: update to proper memory apiAlexander Graf1-90/+48
The openpic code was still using the old mmio memory api. Convert it to be a generic memory api user and clean up some code that becomes redundant that way. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14mpic: Unify numbering schemeAlexander Graf2-249/+45
MPIC interrupt numbers in Linux (device tree) and in QEMU are different, because QEMU takes the sparseness of the IRQ number space into account. Remove that cleverness and instead assume a flat number space. This makes the code easier to understand, because we are actually aligned with Linux on the view of our worlds. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14openpic: Remove unused codeAlexander Graf1-163/+0
The openpic code had a few WIP bits left that nobody reanimated within the last few years. Remove that code. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Hervé Poussineau <hpoussin@reactos.org>
2012-12-14pseries: Don't allow TCE (iommu) tables to be registered with duplicate LIOBNsDavid Gibson1-0/+6
The PAPR specification requires that every bus or device mediated by the IOMMU have a unique Logical IO Bus Number (LIOBN). This patch adds a check to enforce this, which will help catch errors in configuration earlier. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14Adding BAR0 for e500 PCI controllerBharat Bhushan3-10/+91
PCI Root complex have TYPE-1 configuration header while PCI endpoint have type-0 configuration header. The type-1 configuration header have a BAR (BAR0). In Freescale PCI controller BAR0 is used for mapping pci address space to CCSR address space. This can used for 2 purposes: 1) for MSI interrupt generation 2) Allow CCSR registers access when configured as PCI endpoint, which I am not sure is a use case with QEMU-KVM guest. What I observed is that when guest read the size of BAR0 of host controller configuration header (TYPE1 header) then it always reads it as 0. When looking into the QEMU hw/ppce500_pci.c, I do not find the PCI controller device registering BAR0. I do not find any other controller also doing so may they do not use BAR0. There are two issues when BAR0 is not there (which I can think of): 1) There should be BAR0 emulated for PCI Root complex (TYPE1 header) and when reading the size of BAR0, it should give size as per real h/w. 2) Do we need this BAR0 inbound address translation? When BAR0 is of non-zero size then it will be configured for PCI address space to local address(CCSR) space translation on inbound access. The primary use case is for MSI interrupt generation. The device is configured with an address offsets in PCI address space, which will be translated to MSI interrupt generation MPIC registers. Currently I do not understand the MSI interrupt generation mechanism in QEMU and also IIRC we do not use QEMU MSI interrupt mechanism on e500 guest machines. But this BAR0 will be used when using MSI on e500. I can see one more issue, There are ATMUs emulated in hw/ppce500_pci.c, but i do not see these being used for address translation. So far that works because pci address space and local address space are 1:1 mapped. BAR0 inbound translation + ATMU translation will complete the address translation of inbound traffic. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> [agraf: fix double variable assignment w/o read] Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14e500: Adding CCSR memory regionBharat Bhushan1-23/+40
All devices are also placed under CCSR memory region. The CCSR memory region is exported to pci device. The MSI interrupt generation is the main reason to export the CCSR region to PCI device. This put the requirement to move mpic under CCSR region, but logically all devices should be under CCSR. So this patch places all emulated devices under ccsr region. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14pseries: Implement PAPR NVRAMDavid Gibson4-1/+232
The PAPR specification requires a certain amount of NVRAM, accessed via RTAS, which we don't currently implement in qemu. This patch addresses this deficiency, implementing the NVRAM as a VIO device, with some glue to instantiate it automatically based on a machine option. The machine option specifies a drive id, which is used to back the NVRAM, making it persistent. If nothing is specified, the driver instead simply allocates space for the NVRAM, which will not be persistent Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14pseries: Split xics irq configuration from state informationDavid Gibson1-12/+8
Currently the XICS irq controller code has a per-irq state structure which amongst other things includes whether the interrupt is level or message triggered - this is configured by the platform code, and is not directly visible to the guest. This leads to a slightly awkward construct at reset time where we need to reset everything in the state structure _except_ the lsi/msi flag, which needs to retain the information given at platform init time. More importantly this flag will make matching the qemu state to the KVM state for the upcoming in-kernel XICS implementation more awkward. This patch, therefore, removes this flag from the per-irq state structure, instead adding a parallel array giving the lsi/msi configuration per irq. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14pseries: Add tracepoints to the XICS interrupt controllerDavid Gibson1-3/+20
This patch adds tracing / debugging calls to the XICS interrupt controller implementation used on the pseries machine. Signed-off-by: Ben Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14pseries: Allow RTAS tokens without a qemu handlerBen Herrenschmidt1-1/+1
Kernel-based RTAS calls will not have a qemu handler, but will still be registered in qemu in order to be assigned a token number and appear in the device-tree. Let's test for the name being NULL rather than the handler when deciding to skip an entry while building the device-tree Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14pseries: Return the token when we register an RTAS callMichael Ellerman2-3/+3
The kernel will soon be able to service some RTAS calls. However the choice of tokens will still be up to userspace. To support this have spapr_rtas_register() return the token that is allocated for an RTAS call, that allows the calling code to tell the kernel what the token value is. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14pseries: Use #define for XICS base irq numberBen Herrenschmidt3-2/+3
Currently the lowest "real" irq number for the XICS irq controller (as opposed to numbers reserved for IPIs and other special purposes) is hard coded as 16 in two places - in xics_system_init() and in spapr.c. As well as being generally bad practice, we're going to need to change this number soon to fit in with the in-kernel XICS implementation. This patch adds a #define for this number to avoid future breakage. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Ben Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-14pseries: Fix incorrect initialization of interrupt controllerDavid Gibson1-1/+1
Currently in the reset code for the XICS interrupt controller, we initialize the pending_priority field to 0 (most favored, by XICS convention). This is incorrect, since there is no pending interrupt, it should be set to least favored - 0xff. At the moment our XICS implementation doesn't get hurt by this edge case, but it does confuse the upcoming kernel XICS implementation. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-13Merge remote-tracking branch 'kwolf/for-anthony' into stagingAnthony Liguori18-47/+33
* kwolf/for-anthony: (43 commits) qcow2: Factor out handle_dependencies() qcow2: Execute run_dependent_requests() without lock qcow2: Enable dirty flag in qcow2_alloc_cluster_link_l2 qcow2: Allocate l2meta only for cluster allocations qcow2: Drop l2meta.cluster_offset qcow2: Allocate l2meta dynamically qcow2: Introduce Qcow2COWRegion qcow2: Round QCowL2Meta.offset down to cluster boundary atapi: reset cdrom tray statuses on ide_reset qemu-iotests: Test concurrent cluster allocations qcow2: Move BLKDBG_EVENT out of the lock qemu-io: Add AIO debugging commands blkdebug: Implement suspend/resume of AIO requests blkdebug: Factor out remove_rule() blkdebug: Allow usage without config file create new function: qemu_opt_set_number use qemu_opts_create_nofail introduce qemu_opts_create_nofail function qemu-option: qemu_opt_set_bool(): fix code duplication qemu-option: qemu_opts_validate(): fix duplicated code ... Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-12-13Merge remote-tracking branch 'pmaydell/arm-devs.next' into stagingAnthony Liguori9-37/+106
* pmaydell/arm-devs.next: hw/ds1338.c: Fix handling of DAY (wday) register. hw/ds1338.c: Implement support for the control register. hw/ds1338.c: Ensure state is properly initialized. hw/ds1338.c: Fix handling of HOURS register. hw/ds1338.c: Add definitions for various flags in the RTC registers. hw/ds1338.c: Correct bug in conversion to BCD. exynos4210/mct: Avoid infinite loop on non incremental timers hw/arm_gic: fix target CPUs affected by set enable/pending ops xilinx_zynq: Add one variable to avoid overwriting QSPI bus hw/arm_gic_common: Correct GICC_PMR reset value for newer GICs hw/arm_gic: Fix comparison with priority mask register hw/arm_boot, exynos4210, highbank: Fix secondary boot GIC init Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-12-13hw/ds1338.c: Fix handling of DAY (wday) register.Antoine Mathys1-3/+12
Per the datasheet, the DAY (wday) register is user defined. Implement this. Signed-off-by: Antoine Mathys <barsamin@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-12-13hw/ds1338.c: Implement support for the control register.Antoine Mathys1-4/+13
Signed-off-by: Antoine Mathys <barsamin@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-12-13hw/ds1338.c: Ensure state is properly initialized.Antoine Mathys1-0/+12
Signed-off-by: Antoine Mathys <barsamin@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-12-13hw/ds1338.c: Fix handling of HOURS register.Antoine Mathys1-11/+18
Per the datasheet, the mapping between 12 and 24 hours modes is: 0 <-> 12 PM 1-12 <-> 1-12 AM 13-23 <-> 1-11 PM Signed-off-by: Antoine Mathys <barsamin@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-12-13hw/ds1338.c: Add definitions for various flags in the RTC registers.Antoine Mathys1-0/+6
Signed-off-by: Antoine Mathys <barsamin@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-12-13hw/ds1338.c: Correct bug in conversion to BCD.Antoine Mathys1-2/+2
Signed-off-by: Antoine Mathys <barsamin@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-12-13atapi: reset cdrom tray statuses on ide_resetPavel Hrdina1-0/+2
Tray statuses should be also reseted. Some guests may lock the tray and after reset before any kernel is loaded the tray should be unlocked. Also if you reset the real computer the tray is closed. We should do the same in qemu. Signed-off-by: Pavel Hrdina <phrdina@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2012-12-12pci: prepare makefiles for pci code reorganizationMichael S. Tsirkin1-0/+1
To make it easier to move code around without breaking build at intermedite steps, tweak makefiles to look in pci/ and hw/ for include files, automatically. This will be reverted at the end of the reorganization. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2012-12-12Fixup q35/ich9 LicensesJason Baron3-36/+23
Cleanup the q35/ich9 license headers. Signed-off-by: Jason Baron <jbaron@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Isaku Yamahata <yamahata@valinux.co.jp>
2012-12-11use qemu_opts_create_nofailDong Xu Wang1-1/+1
We will use qemu_opts_create_nofail function, it can make code more readable. Signed-off-by: Dong Xu Wang <wdongxu@linux.vnet.ibm.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2012-12-11exynos4210/mct: Avoid infinite loop on non incremental timersJean-Christophe DUBOIS1-1/+1
Check for a 0 "distance" value to avoid infinite loop when the expired FCR timer was not programed with auto-increment. With this change the behavior is coherent with the same type of code in the exynos4210_gfrc_restart() function in the same file. Linux seems to mostly use this timer with auto-increment which explain why it is not a problem most of the time. However other OS might have a problem with this if they don't use the auto-increment feature. Signed-off-by: Jean-Christophe DUBOIS <jcd@tribudubois.net> Reviewed-by: Evgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-12-11hw/arm_gic: fix target CPUs affected by set enable/pending opsDaniel Sangorrin1-2/+3
Fix a bug on the ARM GIC model where interrupts are not set pending on the correct target CPUs when they are triggered by writes to the Interrupt Set Enable or Set Pending registers. Signed-off-by: Daniel Sangorrin <dsl@ertl.jp> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-12-11xilinx_zynq: Add one variable to avoid overwriting QSPI buswalimis1-4/+5
commit 7b482bcf xilinx_zynq: added QSPI controller Adds one QSPI controller, which has two spi buses, one is for spi0, and another is for spi1. But when initializing the spi1 bus, "dev" has been overwrited by the ssi_create_slave_no_init() function, so that qdev_get_child_bus() returns NULL and the last two m25p80 flashes won't be attached to the spi1 bus, but to main-system-bus. Here we add one variable to avoid overwriting. Signed-off-by: Liming Wang <walimisdev@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-12-11hw/arm_gic_common: Correct GICC_PMR reset value for newer GICsPeter Maydell2-2/+8
The GIC architecture specification for v1 and v2 GICs (as found on the Cortex-A9 and newer) states that the GICC_PMR reset value is zero; this differs from the 0xf0 reset value used on 11MPCore. The NVIC is different again in not having a CPU interface; since we share the GIC code we must force the priority mask field to allow through all interrupts. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Igor Mitsyanko <i.mitsyanko@samsung.com>
2012-12-11hw/arm_gic: Fix comparison with priority mask registerPeter Maydell1-1/+1
The GIC spec states that only interrupts with higher priority than the value in the GICC_PMR priority mask register are passed through to the processor. We were incorrectly allowing through interrupts with a priority equal to the specified value: correct the comparison operation to match the spec. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Igor Mitsyanko <i.mitsyanko@samsung.com>
2012-12-11hw/arm_boot, exynos4210, highbank: Fix secondary boot GIC initPeter Maydell3-8/+26
Fix the code in the secondary CPU boot stubs so that it correctly initialises the GIC rather than relying on bugs or implementation dependent aspects of the QEMU GIC implementation: * set the GIC_PMR.Priority field to all-ones, so that all interrupts are passed through. The default of all-zeroes means all interrupts are masked, and QEMU only booted because of a bug in the priority masking in our GIC implementation. * add a barrier after GIC setup and before WFI to ensure that GIC config is complete before we go into a possible low power state. This isn't needed with the software GIC model but could be required when using KVM and executing this code on the real hardware CPU. Note that of the three secondary stub implementations, only the common generic one needs to support both v6 and v7 DSB encodings; highbank and exynos4210 will always be v7 CPUs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Igor Mitsyanko <i.mitsyanko@samsung.com>
2012-12-11Support default block interfaces per QEMUMachineChristian Borntraeger14-44/+30
There are QEMUMachines that have neither IF_IDE nor IF_SCSI as a default/standard interface to their block devices / drives. Therefore, this patch introduces a new field default_block_type per QEMUMachine struct. The prior use_scsi field becomes thereby obsolete and is replaced through .default_block_type = IF_SCSI. This patch also changes the default for s390x to IF_VIRTIO and removes an early hack that converts IF_IDE drives. Other parties have already claimed interest (e.g. IF_SD for exynos) To create a sane default, for machines that dont specify a default_block_type, this patch makes IF_IDE = 0 and IF_NONE = 1. I checked all users of IF_NONE (blockdev.c and ww/device-hotplug.c) as well as IF_IDE and it seems that it is ok to change the defines - in other words, I found no obvious (to me) assumption in the code regarding IF_NONE==0. IF_NONE is only set if there is an explicit if=none. Without if=* the interface becomes IF_DEFAULT. I would suggest to have some additional care, e.g. by letting this patch sit some days in the block tree. Based on an initial patch from Einar Lueck <elelueck@de.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> CC: Igor Mitsyanko <i.mitsyanko@samsung.com> CC: Markus Armbruster <armbru@redhat.com> CC: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Alexander Graf <agraf@suse.de> Acked-by: Igor Mitsyanko <i.mitsyanko@samsung.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-12-11virtio-blk: Remove duplicate property definitionDavid Gibson2-2/+0
For the virtio-blk device (via virtio-pci) the property "config-wce" is defined in two places. First, it's defined from the DEFINE_VIRTIO_BLK_FEATURES macro, second it's defined directly in virtio-pci, just two lines above the call to that macro. The direct definition in virtio-pci.c is broken, since it operates on the 'config_wce' field of VirtIOBlkConf, which is never used anywhere else. Therefore, this patch removes both the extra property definition and the redundant field it works on. Cc: Kevin Wolf <kwolf@redhat.com> Cc: Anthony Liguori <aliguori@us.ibm.com> Cc: Paul 'Rusty' Russell <rusty@rustcorp.com.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-12-10vfio-pci: Don't use kvm_irqchip_in_kernelAlex Williamson1-2/+3
kvm_irqchip_in_kernel() has an architecture specific meaning, so we shouldn't be using it to determine whether to enabled KVM INTx bypass. kvm_irqfds_enabled() seems most appropriate. Also use this to protect our other call to kvm_check_extension() as that explodes when KVM isn't enabled. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Cc: qemu-stable@nongnu.org
2012-12-10Merge remote-tracking branch 'afaerber/qom-cpu' into stagingAnthony Liguori2-13/+6
* afaerber/qom-cpu: target-i386: Postpone cpuid_level update to realize time target-i386: Use define for cpuid vendor string size target-i386: Separate feature string parsing from CPU model lookup target-i386/cpu.c: Coding style fixes qdev: qdev_create(): use error_report() instead of hw_error() sysemu.h: Include qemu-types.h instead of qemu-common.h Create qemu-types.h for struct typedefs qlist.h: Do not include qemu-common.h qga/channel-posix.c: Include headers it needs qapi/qmp-registry.c: Include headers it needs ui/vnc-palette.c: Include headers it needs user: Rename qemu-types.h to qemu-user-types.h user: Move *-user/qemu-types.h to main directory Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-12-10Merge remote-tracking branch 'stefanha/trivial-patches' into stagingAnthony Liguori8-22/+19
* stefanha/trivial-patches: pc_sysfw: Plug memory leak on pc_fw_add_pflash_drv() error path qemu-options: Fix space at EOL Fix spelling in comments and documentation Clean up pci_drive_hot_add()'s use of BlockInterfaceType arm: a9mpcore: remove un-used ptimer_iomem field target-sparc: Remove t0, t1 from CPUSPARCState target-m68k: Remove t1 from CPUM68KState target-alpha: Remove t0, t1 from CPUAlphaState s390x: Spelling fixes (endianess -> endianness, occured -> occurred) Fix comments (adress -> address, layed -> laid, wierd -> weird) Fix spelling (prefered -> preferred) configure: Remove stray debug output sd: Send debug printfery to stderr not stdout Conflicts: configure Resolve spelling conflict in configure. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-12-10Merge remote-tracking branch 'kraxel/acpi.1' into stagingAnthony Liguori11-415/+317
* kraxel/acpi.1: acpi: drop debug port q35: update lpc pci config space according to configured devices apci: switch piix4 pci hotplug to memory api acpi: remove acpi_gpe_blk apci: switch piix4 gpe to memory api acpi: fix piix4 smbus mapping acpi: switch smbus to memory api acpi: cleanup ich9 memory region apci: switch ich9 smi to memory api apci: switch ich9 gpe to memory api acpi: cleanup vt82c686 memory region acpi: cleanup piix4 memory region apci: switch evt to memory api apci: switch cnt to memory api apci: switch timer to memory api apci: switch vt82c686 to memory api apci: switch ich9 to memory api apci: switch piix4 to memory api Conflicts: hw/lpc_ich9.c Resolved merge conflict due to apm_init adding an argument. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-12-10Merge remote-tracking branch 'kraxel/usb.74' into stagingAnthony Liguori13-9/+168
* kraxel/usb.74: usb-tablet: Allow connecting to ehci ehci: Lower timer freq when the periodic schedule is idle usb: Allow overriding of usb_desc at the device level usb: Don't allow USB_RET_ASYNC for interrupt packets usb: Call wakeup when data becomes available for all devices with int eps add pc-1.4 Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-12-08Merge branch 'master' of git.qemu-project.org:/pub/git/qemuBlue Swirl2-5/+6
* 'master' of git.qemu-project.org:/pub/git/qemu: target-mips: Fix incorrect shift for SHILO and SHILOV target-mips: Fix incorrect code and test for INSV xilinx_uartlite: Accept input after rx FIFO pop xilinx_uartlite: suppress "cannot receive message" xilinx_axienet: Implement R_IS behaviour
2012-12-07pc_sysfw: Plug memory leak on pc_fw_add_pflash_drv() error pathMarkus Armbruster1-1/+3
Harmless, because we the error inevitably leads to another, fatal one in pc_system_flash_init(): PC system firmware (pflash) not available. Fix it anyway. Signed-off-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-12-07Fix spelling in comments and documentationStefan Weil1-3/+3
These spelling bugs were found by codespell: supressing -> suppressing transfered -> transferred Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-12-07Clean up pci_drive_hot_add()'s use of BlockInterfaceTypeMarkus Armbruster2-11/+7
pci_drive_hot_add() parameter type has the wrong type: int instead of BlockInterfaceType. It's actually redundant, so we can just drop it. Signed-off-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-12-07arm: a9mpcore: remove un-used ptimer_iomem fieldPeter Crosthwaite1-1/+0
I'm guessing this is a hangover from a previous coreification of the mptimer sub-module. This field is completely unused - removed. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-12-07s390x: Spelling fixes (endianess -> endianness, occured -> occurred)Stefan Weil2-4/+4
Replace also "write into" by "write to". Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-12-07sd: Send debug printfery to stderr not stdoutPeter Crosthwaite1-2/+2
Some debug printfs for SD are coming up in stdout. Redirected them to stderr instead. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-12-06qdev: qdev_create(): use error_report() instead of hw_error()Eduardo Habkost1-3/+5
hw_error() is specific for fatal hardware emulation errors, not for internal errors related to the qdev object/class abstraction or object initialization. Replace it with an error_report() call, followed by abort(). This will also help reduce dependencies of the qdev code (as hw_error() is from cpus.o, and depends on the CPU list from exec.o). Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-12-06Create qemu-types.h for struct typedefsEduardo Habkost1-10/+1
Instead of keeping all those struct typedefs in qemu-common.h, move it to a header that can be safely included by other headers, containing only the struct typedefs and not pulling in other dependencies. Also, move some of the qdev-core.h typedefs to the new file, too, so other headers don't need to include qdev-core.h only because of DeviceState and other typedefs. This will help us remove qemu-common.h dependencies from some headers later. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
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