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2013-12-23ACPI/DSDT-CPU: cleanup bogus commentIgor Mammedov1-1/+0
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-23ACPI: Q35 DSDT: fix CPU hotplug GPE0.2 handlerIgor Mammedov1-2/+2
Fix bogus CPU hotplug GPE handler. Make Q35 CPU hotplug GPE handler match PIIX4 one, since CPU hotplug event is triggered by GPE0.2 register. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-23acpi: ich9: allow guest to clear SCI rised by GPEIgor Mammedov1-0/+1
it fixes IRQ storm since guest isn't able to lower SCI IRQ after it has been handled when it clears GPE event. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-23acpi: factor out common pm_update_sci() into acpi coreIgor Mammedov3-43/+24
... and rename it into acpi_update_sci() since it changes SCI on only on PM registers status. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-23acpi: piix4: remove not needed GPE0 maskIgor Mammedov1-2/+1
Hardcoded GPE0 mask isn't really needed. Since GPE0_STS initialized with all bits cleared and only QEMU itself can set bits there (i.e. guest can only clear bits in it). So guest can't triger SCI by setting _STS & _EN bits and there is not reason to mask out not supported _STS bits since they shouldn't be set by QEMU in the first place. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-23hw/i386/pc_sysfw: support two flash drivesLaszlo Ersek1-19/+86
This patch allows the user to usefully specify -drive file=img_1,if=pflash,format=raw,readonly \ -drive file=img_2,if=pflash,format=raw on the command line. The flash images will be mapped under 4G in their reverse unit order -- that is, with their base addresses progressing downwards, in increasing unit order. (The unit number increases with command line order if not explicitly specified.) This accommodates the following use case: suppose that OVMF is split in two parts, a writeable host file for non-volatile variable storage, and a read-only part for bootstrap and decompressible executable code. The binary code part would be read-only, centrally managed on the host system, and passed in as unit 0. The variable store would be writeable, VM-specific, and passed in as unit 1. 00000000ffe00000-00000000ffe1ffff (prio 0, R-): system.flash1 00000000ffe20000-00000000ffffffff (prio 0, R-): system.flash0 (If the guest tries to write to the flash range that is backed by the read-only drive, pflash_update() is never called; various flash programming/erase errors are returned to the guest instead. See the callers of pflash_update(), and the initialization of "pfl->ro", in "hw/block/pflash_cfi01.c".) Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-23pc_piix: document gigabyte_alignMichael S. Tsirkin1-0/+11
Document the logic behind the below/above 4G split. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-23piix: gigabyte alignment for ramGerd Hoffmann1-2/+5
Map 3G (i440fx) of memory below 4G, so the RAM pieces are nicely aligned to gigabyte borders. Keep old memory layout for (a) old machine types and (b) in case all memory fits below 4G and thus we don't have to split RAM into pieces in the first place. The later makes sure this change doesn't take away memory from 32bit guests. So, with i440fx and up to 3.5 GB of memory, all of it will be mapped below 4G. With more than 3.5 GB of memory 3 GB will be mapped below 4G and the remaining amount will be mapped above 4G. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-20spapr: limit numa memory regions by ram sizePaul Mackerras1-4/+16
This makes sure that all NUMA memory blocks reside within RAM or have zero length. Reviewed-by: Thomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20spapr: make sure RMA is in first mode of first memory nodeAlexey Kardashevskiy1-6/+11
The SPAPR specification says that the RMA starts at the LPAR's logical address 0 and is the first logical memory block reported in the LPAR’s device tree. So SLOF only maps the first block and that block needs to span the full RMA. This makes sure that the RMA area is where SLOF expects it. Reviewed-by: Thomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20device_tree: s/qemu_devtree/qemu_fdt globallyPeter Crosthwaite10-213/+214
The qemu_devtree API is a wrapper around the fdt_ set of APIs. Rename accordingly. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> [agraf: also convert hw/arm/virt.c] Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20roms: Flush icache when writing roms to guest memoryAlexander Graf1-0/+7
We use the rom infrastructure to write firmware and/or initial kernel blobs into guest address space. So we're basically emulating the cache off phase on very early system bootup. That phase is usually responsible for clearing the instruction cache for anything it writes into cachable memory, to ensure that after reboot we don't happen to execute stale bits from the instruction cache. So we need to invalidate the icache every time we write a rom into guest address space. We do not need to do this for every DMA since the guest expects it has to flush the icache manually in that case. This fixes random reboot issues on e5500 (booke ppc) for me. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20spapr: tie spapr-nvram to -pflashPaolo Bonzini1-11/+3
spapr-nvram's drive property is currently connected to a non-existent "-machine nvram=<drivename>" option. Instead, tie it to -pflash like other non-volatile RAM devices. This provides the following possibilities for adding a backend for the sPAPR non-volatile RAM: * -pflash filename * -drive if=pflash,file=filename,format=raw,... * -drive if=none,file=filename,format=raw,id=foo,... -global spapr-nvram.drive=foo Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20PPC: Use default pci bus name for grackle and heathrowAlexander Graf2-3/+3
There's no good reason to call our bus "pci" rather than let the default bus name take over ("pci.0"). The big downside to calling it different from anyone else is that tools that pass -device get confused. They are looking for a bus "pci.0" rather than "pci". To make life easier for everyone, let's just drop the name override. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20spapr-rtas: add ibm, (get|set)-system-parameterAlexey Kardashevskiy1-0/+47
This adds very basic handlers for ibm,get-system-parameter and ibm,set-system-parameter RTAS calls. The only parameter handled at the moment is "platform-processor-diagnostics-run-mode" which is always disabled and does not support changing. This is expected to make "ppc64_cpu --run-mode=1" happy. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> [agraf: s/papameter/parameter/g] Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20spapr-rtas: replace return code constants with macrosAlexey Kardashevskiy6-67/+67
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-17hw/arm: add cubieboard supportliguang2-1/+70
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387159292-10436-6-git-send-email-lig.fnst@cn.fujitsu.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17hw/arm: add allwinner a10 SoC supportliguang2-0/+104
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387159292-10436-5-git-send-email-lig.fnst@cn.fujitsu.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17hw/intc: add allwinner A10 interrupt controllerliguang2-0/+201
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1387159292-10436-4-git-send-email-lig.fnst@cn.fujitsu.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17hw/timer: add allwinner a10 timerliguang2-0/+256
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387159292-10436-3-git-send-email-lig.fnst@cn.fujitsu.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17hw/arm/digic: add NOR ROM supportAntony Pavlov1-0/+78
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Message-id: 1387188908-754-6-git-send-email-antonynpavlov@gmail.com [PMM: don't try to load ROM blob if qtest_enabled()] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17hw/arm/digic: add UART supportAntony Pavlov3-0/+212
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387188908-754-5-git-send-email-antonynpavlov@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17hw/arm/digic: add timer supportAntony Pavlov3-0/+192
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387188908-754-4-git-send-email-antonynpavlov@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17hw/arm/digic: prepare DIGIC-based boards supportAntony Pavlov2-0/+85
Also this patch adds initial support for Canon PowerShot A1100 IS compact camera. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Message-id: 1387188908-754-3-git-send-email-antonynpavlov@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17hw/arm: add very initial support for Canon DIGIC SoCAntony Pavlov2-0/+72
DIGIC is Canon Inc.'s name for a family of SoC for digital cameras and camcorders. There is no publicly available specification for DIGIC chips. All information about DIGIC chip internals is based on reverse engineering efforts made by CHDK (http://chdk.wikia.com) and Magic Lantern (http://www.magiclantern.fm) projects contributors. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387188908-754-2-git-send-email-antonynpavlov@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17hw/arm/boot: Add boot support for AArch64 processorMian M. Hamayun1-5/+38
This commit adds support for booting a single AArch64 CPU by setting appropriate registers. The bootloader includes placeholders for Board-ID that are used to implement uniform indexing across different bootloaders. Signed-off-by: Mian M. Hamayun <m.hamayun@virtualopensystems.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1385645602-18662-7-git-send-email-peter.maydell@linaro.org [PMM: * updated to use ARMInsnFixup style bootloader fragments * dropped virt.c additions * use runtime checks for "is this an AArch64 core" rather than ifdefs * drop some unnecessary setting of registers in reset hook ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
2013-12-17hw/arm/boot: Allow easier swapping in of different loader codePeter Maydell1-45/+107
For AArch64 we will obviously require a different set of primary and secondary boot loader code fragments. However currently we hardcode the offsets into the loader code where we must write the entrypoint and other data into arm_load_kernel(). This makes it hard to substitute a different loader fragment, so switch to a more flexible scheme where instead of a raw array of instructions we use an array of (instruction, fixup-type) pairs that indicate which words need special action or data written into them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1385645602-18662-6-git-send-email-peter.maydell@linaro.org Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2013-12-17arm/highbank.c: Fix MPCore periphbase namePeter Crosthwaite1-7/+8
GIC_BASE_ADDR is not the base address of the GIC. Its clear from the code that this is the base address of the MPCore. Rename to MPCORE_PERIPHBASE accordingly. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 90798bd3507205c16238b8b19a1a58c5437cf7ca.1387160489.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17arm/xilinx_zynq: Implement CBAR initialisationPeter Crosthwaite1-1/+8
Fix the CBAR initialisation by using the newly defined static property. Zynq will now correctly init the CBAR to the SCU base address. Needed to boot Linux on the xilinx_zynq machine model. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 8db7d57ebe5418fed397fcc86ea719f98446c178.1387160489.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17arm/xilinx_zynq: Use object_new() rather than cpu_arm_init()Peter Crosthwaite1-3/+9
To allow the machine model to set device properties before CPU realization. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: e57658b4506b26ab6b6fadbe6d7827f669f51895.1387160489.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17arm/highbank: Fix CBAR initialisationPeter Crosthwaite1-3/+5
Fix the CBAR initialisation by using the newly defined static property. CBAR is now set before realization, so the intended value is now actually used. So I have kind of tested this. I booted an ARM kernel on Highbank with the stock Highbank DTB. It doesn't boot (and I will be doing something wrong), but before this patch I got this: ------------[ cut here ]------------ WARNING: CPU: 0 PID: 0 at /workspaces/pcrost/public/linux2.git/arch/arm/mm/ioremap.c:301 __arm_ioremap_pfn_caller+0x180/0x198() CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 3.13.0-rc1-next-20131126-dirty #2 [<c0015164>] (unwind_backtrace) from [<c00118c0>] (show_stack+0x10/0x14) [<c00118c0>] (show_stack) from [<c02bd5fc>] (dump_stack+0x78/0x90) [<c02bd5fc>] (dump_stack) from [<c001f110>] (warn_slowpath_common+0x68/0x84) [<c001f110>] (warn_slowpath_common) from [<c001f1f4>] (warn_slowpath_null+0x1c/0x24) [<c001f1f4>] (warn_slowpath_null) from [<c0017c6c>] (__arm_ioremap_pfn_caller+0x180/0x198) [<c0017c6c>] (__arm_ioremap_pfn_caller) from [<c0017cd8>] (__arm_ioremap_caller+0x54/0x5c) [<c0017cd8>] (__arm_ioremap_caller) from [<c0017d10>] (__arm_ioremap+0x18/0x1c) [<c0017d10>] (__arm_ioremap) from [<c03913c0>] (highbank_init_irq+0x34/0x8c) [<c03913c0>] (highbank_init_irq) from [<c038c228>] (init_IRQ+0x28/0x2c) [<c038c228>] (init_IRQ) from [<c03899ec>] (start_kernel+0x234/0x398) [<c03899ec>] (start_kernel) from [<00008074>] (0x8074) ---[ end trace 3406ff24bd97382f ]--- Which disappears with this patch. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: fedec366aaa512d75093635f523d1dbcb3358361.1387160489.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17arm/highbank: Use object_new() rather than cpu_arm_init()Peter Crosthwaite1-3/+9
To allow the machine model to set device properties before CPU realization. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 8c671e500390c8be0cc363e887e32867d1d1b0d2.1387160489.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17Fix NOR flash device ID readingRoy Franz2-23/+88
Fix NOR flash manufacturer and device ID reading. This now properly takes into account device widths and device max widths as required. The reading of these IDs uses the same max_width dependent addressing as CFI queries. The old code remains for chips that don't specify a device width, as the new code relies on a device width being set in order to properly operate. The existing code seems very broken. Only ident0 and ident1 are used in the new code, as other fields relate to the lock state of blocks in flash. The VExpress flash configuration has been updated to match the new code, as the existing definition was 'wrong' in order to return the expected results with the broken device ID code. Signed-off-by: Roy Franz <roy.franz@linaro.org> Message-id: 1386279359-32286-8-git-send-email-roy.franz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17Fix CFI query responses for NOR flashRoy Franz1-11/+94
This change fixes the CFI query responses to handle NOR device widths that are different from the bank width. Support is also added for multi-width devices in a x8 configuration. This is typically x8/x16 devices, but the CFI specification mentions x8/x32 devices so those should be supported as well if they exist. The query response data is now replicated per-device in the bank, and is adjusted for x16 or x32 parts configured in x8 mode. The existing code is left in place for boards that have not been updated to specify an explicit device_width. The VExpress board has been updated in an earlier patch in this series so this is the only board currently affected. Signed-off-by: Roy Franz <roy.franz@linaro.org> Message-id: 1386279359-32286-7-git-send-email-roy.franz@linaro.org [PMM: fixed a few formatting nits] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17Add max device width parameter for NOR devicesRoy Franz1-0/+25
For handling CFI and device ID reads, we need to not only know the width that a NOR flash device is configured for, but also its maximum width. The maximum width addressing mode is used for multi-width parts no matter which width they are configured for. The most common case is x16 parts that also support x8 mode. When configured for x8 operation these devices respond to CFI and device ID requests differently than native x8 NOR parts. Signed-off-by: Roy Franz <roy.franz@linaro.org> Message-id: 1386279359-32286-6-git-send-email-roy.franz@linaro.org [PMM: Added comment explaining the semantics of width vs device-width vs max-device-width] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17Set proper device-width for vexpress flashRoy Franz1-10/+34
Create vexpress specific pflash registration function which properly configures the device-width of 16 bits (2 bytes) for the NOR flash on the vexpress platform. This change is required for buffered flash writes to work properly. Signed-off-by: Roy Franz <roy.franz@linaro.org> Message-id: 1386279359-32286-5-git-send-email-roy.franz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17return status for each NOR flash deviceRoy Franz1-2/+13
Now that we know how wide each flash device that makes up the bank is, return status for each device in the bank. Leave existing code that treats 32 bit wide banks as composed of two 16 bit devices as otherwise we may break configurations that do not set the device_width propery. Signed-off-by: Roy Franz <roy.franz@linaro.org> Message-id: 1386279359-32286-4-git-send-email-roy.franz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17Add device-width property to pflash_cfi01Roy Franz1-0/+11
The width of the devices that make up the flash interface is required to mask certain commands, in particular the write length for buffered writes. This length will be presented to each device on the interface by the program writing the flash, and the flash emulation code needs to be able to determine the length of the write as recieved by each flash device. The device-width defaults to the bank width which should maintain existing behavior for platforms that don't need this change. This change is required to support buffered writes on the vexpress platform that has a 32 bit flash interface with 2 16 bit devices on it. Signed-off-by: Roy Franz <roy.franz@linaro.org> Message-id: 1386279359-32286-3-git-send-email-roy.franz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17rename pflash_t member width to bank_widthRoy Franz1-8/+9
Rename the 'width' member of the pflash_t structure in preparation for adding a bank_width member. Signed-off-by: Roy Franz <roy.franz@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1386279359-32286-2-git-send-email-roy.franz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-16spice: stop server for qxl hard resetGerd Hoffmann1-0/+10
Hard reset can happen at any time. We should be able to put qxl into a known-good state no matter what. Stop spice server thread for reset so it can't be confused by fetching stale commands lingering around in the rings while we reset is ongoing. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2013-12-13Merge remote-tracking branch 'bonzini/virtio' into stagingAnthony Liguori17-320/+387
# By Andreas Färber (18) and Paolo Bonzini (12) # Via Paolo Bonzini * bonzini/virtio: (30 commits) virtio: Convert exit to unrealize virtio: Complete converting VirtioDevice to QOM realize virtio-scsi: Convert to QOM realize virtio-rng: Convert to QOM realize virtio-balloon: Convert to QOM realize virtio-net: Convert to QOM realize virtio-serial: Convert to QOM realize virtio-blk: Convert to QOM realize virtio-9p: Convert to QOM realize virtio: Start converting VirtioDevice to QOM realize virtio-scsi: QOM realize preparations virtio-rng: QOM realize preparations virtio-balloon: QOM realize preparations virtio-net: QOM realize preparations virtio-serial: QOM realize preparations virtio-blk: QOM realize preparations virtio-9p: QOM realize preparations virtio-blk-dataplane: Improve error reporting virtio-pci: add device_unplugged callback virtio-rng: switch exit callback to VirtioDeviceClass ...
2013-12-13Merge remote-tracking branch 'mst/tags/for_anthony' into stagingAnthony Liguori15-91/+135
acpi.pci,pc,memory core fixes Most notably this includes changes to exec to support full 64 bit addresses. This also flushes out patches that got queued during 1.7 freeze. There are new tests, and a bunch of bug fixes all over the place. There are also some changes mostly useful for downstreams. I'm also listing myself as pc co-maintainer. I'm doing this reluctantly, but this seems to be necessary to make sure patches are not lost or delayed too much, and posting the MAINTAINERS patch did not seem to make anyone else volunteer. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Wed 11 Dec 2013 10:21:51 AM PST using RSA key ID D28D5469 # gpg: Can't check signature: public key not found # By Michael S. Tsirkin (14) and others # Via Michael S. Tsirkin * mst/tags/for_anthony: (28 commits) pc: use macro for HPET type hpet: fix build with CONFIG_HPET off acpi unit-test: adjust the test data structure for better handling acpi unit-test: load and check facs table exec: separate sections and nodes per address space memory.c: bugfix - ref counting mismatch in memory_region_find hpet: enable to entitle more irq pins for hpet hpet: inverse polarity when pin above ISA_NUM_IRQS pci: fix pci bridge fw path ACPI DSDT: Make control method `IQCR` serialized acpi: strip compiler info in built-in DSDT acpi unit-test: verify signature and checksum smbios: Set system manufacturer, product & version by default exec: reduce L2_PAGE_SIZE exec: make address spaces 64-bit wide exec: memory radix tree page level compression exec: pass hw address to phys_page_find exec: extend skip field to 6 bit, page entry to 32 bit exec: replace leaf with skip split definitions for exec.c and translate-all.c radix trees ... Message-id: cover.1386786228.git.mst@redhat.com Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-12-13Merge remote-tracking branch 'bonzini/scsi-next' into stagingAnthony Liguori2-9/+34
# By Paolo Bonzini (4) and Peter Lieven (1) # Via Paolo Bonzini * bonzini/scsi-next: help: add id suboption to -iscsi scsi-disk: fix WRITE SAME with large non-zero payload block/iscsi: introduce bdrv_co_{readv, writev, flush_to_disk} scsi-disk: fix VERIFY emulation scsi-bus: fix transfer length and direction for VERIFY command Message-id: 1386594157-17535-1-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-12-11pc: use macro for HPET typeMichael S. Tsirkin1-1/+1
avoid hard-coding strings Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-11hpet: fix build with CONFIG_HPET offMichael S. Tsirkin1-6/+0
make hpet_find inline so we don't need to build hpet.c to check if hpet is enabled. Fixes link error with CONFIG_HPET off. Cc: qemu-stable@nongnu.org Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-11hpet: enable to entitle more irq pins for hpetLiu Ping Fan4-10/+33
Owning to some different hardware design, piix and q35 need different compat. So making them diverge. On q35, IRQ2/8 can be reserved for hpet timer 0/1. And pin 16~23 can be assigned to hpet as guest chooses. So we introduce intcap property to do that. Consider the compat and piix/q35, we finally have the following value for intcap: For piix, hpet's intcap is hard coded as IRQ2. For pc-q35-1.7 and earlier, we use IRQ2 for compat reason. Otherwise IRQ2, IRQ8, and IRQ16~23 are allowed. Signed-off-by: Liu Ping Fan <pingfank@linux.vnet.ibm.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-11hpet: inverse polarity when pin above ISA_NUM_IRQSLiu Ping Fan1-2/+12
According to hpet spec, hpet irq is high active. But according to ICH spec, there is inversion before the input of ioapic. So the OS will expect low active on this IRQ line. (On bare metal, if OS driver claims high active on this line, spurious irq is generated) We fold the emulation of this inversion inside the hpet logic. Signed-off-by: Liu Ping Fan <pingfank@linux.vnet.ibm.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-11pci: fix pci bridge fw pathGerd Hoffmann1-1/+1
qemu uses "pci" as name for pci bridges in the firmware device path. seabios expects "pci-bridge". Result is that bootorder is broken for devices behind pci bridges. Some googling suggests that "pci-bridge" is the correct one. At least PPC-based Apple machines are using this. See question "How do I boot from a device attached to a PCI card" here: http://www.netbsd.org/ports/macppc/faq.html So lets change qemu to use "pci-bridge" too. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2013-12-10Merge remote-tracking branch 'stefanha/net-next' into stagingAnthony Liguori1-15/+20
# By Vincenzo Maffione (2) and others # Via Stefan Hajnoczi * stefanha/net-next: net: Update netdev peer on link change virtio-net: don't update mac_table in error state MAINTAINERS: Add netmap maintainers net: Adding netmap network backend Message-id: 1386594692-21278-1-git-send-email-stefanha@redhat.com Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-12-10Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20131210' into ↵Anthony Liguori8-131/+1060
staging target-arm queue: * support REFCNT register on integrator/cp board * implement the A9MP's global timer * add the 'virt' platform * support '-cpu host' on KVM/ARM * Cadence GEM ethernet device bugfixes * Implement 32-bit ARMv8 VSEL, VMAXNM, VMINNM * fix TTBCR write masking * update 32 bit decoder to use new qemu_ld/st TCG opcodes # gpg: Signature made Tue 10 Dec 2013 06:22:01 AM PST using RSA key ID 14360CDE # gpg: Can't check signature: public key not found # By Peter Crosthwaite (16) and others # Via Peter Maydell * pmaydell/tags/pull-target-arm-20131210: (37 commits) target-arm: fix TTBCR write masking target-arm: Use new qemu_ld/st opcodes target-arm: Implement ARMv8 SIMD VMAXNM and VMINNM instructions. target-arm: Implement ARMv8 FP VMAXNM and VMINNM instructions. softfloat: Add minNum() and maxNum() functions to softfloat. softfloat: Remove unused argument from MINMAX macro. target-arm: Implement ARMv8 VSEL instruction. target-arm: Move call to disas_vfp_insn out of disas_coproc_insn. net/cadence_gem: Don't rx packets when no rx buffer available net/cadence_gem: Improve can_receive debug printfery net/cadence_gem: Fix register w1c logic net/cadence_gem: Fix small packet FCS stripping net/cadence_gem: Fix rx multi-fragment packets net/cadence_gem: Add missing VMSTATE_END_OF_LIST net/cadence_gem: Implement SAR (de)activation net/cadence_gem: Implement SAR match bit in rx desc net/cadence_gem: Implement RX descriptor match mode flags net/cadence_gem: Prefetch rx descriptors ASAP net/cadence_gem: simplify rx buf descriptor walking net/cadence_gem: Don't assert against 0 buffer address ... Message-id: 1386686613-2390-1-git-send-email-peter.maydell@linaro.org Signed-off-by: Anthony Liguori <aliguori@amazon.com>
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