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2013-07-29xics: rename types to be sane and follow coding styleAnthony Liguori2-112/+261
Basically, in HW the layout of the interrupt network is: - One ICP per processor thread (the "presenter"). This contains the registers to fetch a pending interrupt (ack), EOI, and control the processor priority. - One ICS per logical source of interrupts (ie, one per PCI host bridge, and a few others here or there). This contains the per-interrupt source configuration (target processor(s), priority, mask) and the per-interrupt internal state. Under PAPR, there is a single "virtual" ICS ... somewhat (it's a bit oddball what pHyp does here, arguably there are two but we can ignore that distinction). There is no register level access. A pair of firmware (RTAS) calls is used to configure each virtual interrupt. So our model here is somewhat the same. We have one ICS in the emulated XICS which arguably *is* the emulated XICS, there's no point making it a separate "device", that would just be gross, and each VCPU has an associated ICP. Yet we call the "XICS" struct icp_state and then the ICPs 'struct icp_server_state'. It's particularly confusing when all of the functions have xics_prefixes yet take *icp arguments. Rename: struct icp_state -> XICSState struct icp_server_state -> ICPState struct ics_state -> ICSState struct ics_irq_state -> ICSIRQState Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Message-id: 1374175984-8930-12-git-send-email-aliguori@us.ibm.com [aik: added ics_resend() on post_load] Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-29pseries: savevm support with KVMAlexey Kardashevskiy1-22/+84
At present, the savevm / migration support for the pseries machine will not work when KVM is enabled. That's because KVM manages the guest's hash page table in the host kernel, so qemu has no visibility of it. This patch fixes this by using new kernel interfaces to extract and reinsert the guest's hash table during the migration process. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Message-id: 1374175984-8930-11-git-send-email-aliguori@us.ibm.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-29pseries: savevm support for PCI host bridgeDavid Gibson1-0/+49
This adds the necessary support for saving the state of the PAPR virtual PCI host bridge (or host bridges). Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374175984-8930-10-git-send-email-aliguori@us.ibm.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-29pseries: savevm support for pseries machineDavid Gibson2-5/+272
This adds the necessary pieces to implement savevm / migration for the pseries machine. The most complex part here is migrating the hash table - for the paravirtualized pseries machine the guest's hash page table is not stored within guest memory, but externally and the guest accesses it via hypercalls. This patch uses a hypervisor reserved bit of the HPTE as a dirty bit (tracking changes to the HPTE itself, not the page it references). This is used to implement a live migration style incremental save and restore of the hash table contents. Normally a hash table is 16MB but it can get bigger depending on how much RAM the guest has. Due to its nature, updates to it are random so the live migration style is used for it. In addition it adds VMStateDescription information to save and restore the (few) remaining pieces of state information needed by the pseries machine. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374175984-8930-9-git-send-email-aliguori@us.ibm.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-29pseries: savevm support for PAPR virtual SCSIDavid Gibson1-1/+81
This patch adds the necessary support for saving the state of the PAPR VIO virtual SCSI device. This also saves and restores active SCSI requests. [aik: implemented vscsi_req save/restore] Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Message-id: 1374175984-8930-8-git-send-email-aliguori@us.ibm.com Cc: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-29pseries: rework PAPR virtual SCSIAlexey Kardashevskiy1-93/+130
The patch reimplements handling of indirect requests in order to simplify upcoming live migration support. - all pointers (except SCSIRequest*) were replaces with integer indexes and offsets; - DMA'ed srp_direct_buf kept untouched (ie. BE format); - vscsi_fetch_desc() is added, now it is the only place where descriptors are fetched and byteswapped; - vscsi_req struct fields converted to migration-friendly types; - many dprintf()'s fixed. This also removed an unused field 'lun' from the spapr_vscsi device which is assigned, but never used. So, remove it. [David Gibson: removed unused 'lun'] Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Message-id: 1374175984-8930-7-git-send-email-aliguori@us.ibm.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-29spapr-tce: make sPAPRTCETable a proper deviceAnthony Liguori4-54/+99
Model TCE tables as a device that's hooked up as a child object to the owner. Besides the code cleanup, we get a few nice benefits: 1) free actually works now (it was dead code before) 2) the TCE information is visible in the device tree 3) we can expose table information as properties such that if we change the window_size, we can use globals to keep migration working. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Message-id: 1374175984-8930-6-git-send-email-aliguori@us.ibm.com [dwg: pseries: savevm support for PAPR TCE tables] Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> [alexey: ppc kvm: fix to compile] Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-29pseries: savevm support for PAPR VIO logical ttyDavid Gibson1-0/+16
This patch adds the necessary VMStateDescription information to support savevm/loadvm for the spapr_tty (PAPR logical serial) device. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374175984-8930-5-git-send-email-aliguori@us.ibm.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-29pseries: savevm support for PAPR VIO logical lanDavid Gibson1-2/+22
This patch adds the necessary VMStateDescription information to support savevm/loadvm for the spapr_llan (PAPR logical lan) device. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374175984-8930-4-git-send-email-aliguori@us.ibm.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-29pseries: savevm support for VIO devicesDavid Gibson1-0/+20
This patch adds helpers to allow PAPR VIO devices to save state common to all VIO devices during savevm. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374175984-8930-3-git-send-email-aliguori@us.ibm.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-29Merge remote-tracking branch 'sstabellini/xen-130729' into stagingAnthony Liguori3-2/+145
# By Paul Durrant (1) and Stefano Stabellini (1) # Via Stefano Stabellini * sstabellini/xen-130729: Xen PV Device xen_disk: support "direct-io-safe" backend option Message-id: 1375096790-12815-1-git-send-email-stefano.stabellini@eu.citrix.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-29Xen PV DevicePaul Durrant2-1/+132
Introduces a new Xen PV PCI device which will act as a binding point for PV drivers for Xen. The device has parameterized vendor-id, device-id and revision to allow to be configured as a binding point for any vendor's PV drivers. Signed-off-by: Paul Durrant <paul.durrant@citrix.com> Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Reviewed-by: Andreas Färber <afaerber@suse.de>
2013-07-29xen_disk: support "direct-io-safe" backend optionStefano Stabellini1-1/+13
Support backend option "direct-io-safe". This is documented as follows in the Xen backend specification: * direct-io-safe * Values: 0/1 (boolean) * Default Value: 0 * * The underlying storage is not affected by the direct IO memory * lifetime bug. See: * http://lists.xen.org/archives/html/xen-devel/2012-12/msg01154.html * * Therefore this option gives the backend permission to use * O_DIRECT, notwithstanding that bug. * * That is, if this option is enabled, use of O_DIRECT is safe, * in circumstances where we would normally have avoided it as a * workaround for that bug. This option is not relevant for all * backends, and even not necessarily supported for those for * which it is relevant. A backend which knows that it is not * affected by the bug can ignore this option. * * This option doesn't require a backend to use O_DIRECT, so it * should not be used to try to control the caching behaviour. Also, BDRV_O_NATIVE_AIO is ignored if BDRV_O_NOCACHE, so clarify the default flags passed to the qemu block layer. The original proposal for a "cache" backend option has been dropped because it was believed too wide, especially considering that at the moment the backend doesn't have a way to tell the toolstack that it is capable of supporting it. Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Signed-off-by: Ian Jackson <Ian.Jackson@eu.citrix.com>
2013-07-29s390/ipl: Fix boot orderChristian Borntraeger1-10/+12
The latest ipl code adaptions collided with some of the virtio refactoring rework. This resulted in always booting the first disk. Let's fix booting from a given ID. The new code also checks for command lines without bootindex to avoid random behaviour when accessing dev_st (==0). Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-29Merge branch 'trivial-patches' of git://git.corpit.ru/qemuAurelien Jarno8-21/+24
* 'trivial-patches' of git://git.corpit.ru/qemu: target-mips: Remove assignment to a variable which is never used misc: Use g_assert_not_reached for code which is expected to be unreachable qemu-options: mention C-a h in the -nographic doc misc: Fix new typos in comments and strings linux-user: correct argument number for sys_mremap and sys_splice PPC: dbdma: macio: Fix format specifiers (build regression) watchdog: Remove break after exit exec: Remove env from list of poisoned names hw/9pfs: Fix potential memory leak and avoid reuse of freed memory timer: make timers_state static aes: Remove unused code (NDEBUG, u16)
2013-07-29mips_malta: fix copy of the 0x1fc00000 regionAurelien Jarno1-2/+2
Copy the whole 0x1fe000000 region into 0x1fc00000, independently of the loaded BIOS size. This fix the MIPS make check tests. Reported-by: Andreas Färber <afaerber@suse.de> Tested-by: Andreas Färber <afaerber@suse.de> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-29hw/mips: align initrd to 64KB to avoid kernel errorJames Hogan4-4/+4
The Linux kernel can be configured to use 64KB pages, but it also requires initrd to be page aligned. Therefore, to be safe, align the initrd to 64KB using a new INITRD_PAGE_MASK rather than TARGET_PAGE_MASK. Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-28pflash_cfi01: duplicate status byte from bits 23:16 for 32bit readsPaul Burton1-0/+3
The firmware commonly used with MIPS Malta boards (YAMON) reads the status of the pflash with a 32bit memory access. On real hardware this results in the status byte being mirrored in the upper 16 bits of the read value. For example if the status byte is represented by SS then the hardware reads 0x00SS00SS. The YAMON firmware compares the status against 32bit values expecting the mirrored value and fails without it. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-28mips_malta: generate SMBUS EEPROM dataPaul Burton1-46/+87
The malta contains 2 EEPROMs, one containing SPD data for the SDRAM and another containing board information such as serial number and MAC address. These are both exposed via the PIIX4 SMBUS. Generating this data and providing it to smbus_eeprom_init will allow YAMON to read a serial number for the board and prevent it from warning that the EEPROM data is invalid. We already have the contents of the SPD EEPROM which are exposed via FPGA I2C accesses, this is provided as part of the SMBUS EEPROM data too for consistency. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-28mips_malta: cap BIOS endian swap length at 0x3e0000 bytesPaul Burton1-1/+1
This preserves the final sector of the pflash which is used by YAMON to hold environment variables. If the endianness of the environment data is swapped then YAMON will fail to load environment variables from pflash. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-28mips_malta: generate SPD EEPROM data at runtimePaul Burton1-3/+57
The SPD EEPROM specifies the amount of memory present in the system and thus its correct contents can only be known at runtime. Calculating parts of the data on init allows the data to accurately reflect the amount of target memory present and allow YAMON to boot with an arbitrary amount of SDRAM. Where possible the SPD data will favor indicating 2 banks of SDRAM rather than 1. For example the default 128MB of target memory will be represented as 2x64MB banks rather than 1x128MB bank. This allows versions of MIPS BIOS code (such as YAMON 2.22 and older) to boot despite a bug preventing them from handling a single bank of SDRAM with the Galileo GT64120 system controller emulated by QEMU. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-28mips_malta: correct reading MIPS revision at 0x1fc00010Paul Burton1-8/+17
Rather than modifying the BIOS code at its original location, copy it for the 0x1fc00000 region & modify the copy. This means the original ROM code is correctly readable at 0x1e000010 whilst the MIPS revision is readable at 0x1fc00010. Additionally the code previously operated on target memory which would later be overwritten by the BIOS image upon CPU reset if the -bios argument was used to specify the BIOS image. This led to the written MIPS revision being lost. Copying using rom_copy when -bios is used fixes this issue. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-28mips_malta: fix BIOS endianness swappingPaul Burton1-2/+5
If the target is little endian (mipsel) then the BIOS image endianness is swapped so that the big endian BIOS binaries commonly produced can be loaded correctly. When using the -bios argument the BIOS is loaded using load_image_targphys, however this doesn't perform the load to target memory immediately. Instead it loads the BIOS file into a struct Rom which will later be written to target memory upon reset. However the endianness conversion was being performed before this, on init, and operating on the target memory which at this point is blank & will later be overwritten by the (big endian) BIOS image. Correct this by operating on the data referenced by struct Rom rather than the target memory when the -bios argument is used. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-28mips_malta: QOM cast cleanupAndreas Färber1-4/+8
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-27misc: Use g_assert_not_reached for code which is expected to be unreachableStefan Weil3-13/+13
The macro g_assert_not_reached is a better self documenting replacement for assert(0) or assert(false). Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-07-27misc: Fix new typos in comments and stringsStefan Weil2-3/+4
All these typos were found by codespell. sould -> should emperical -> empirical intialization -> initialization successfuly -> successfully gaurantee -> guarantee Fix also another error (before before) in the same context. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-07-27PPC: dbdma: macio: Fix format specifiers (build regression)Stefan Weil1-4/+5
Fix a number of warnings for 32 bit builds (tested on MingW and Linux): CC hw/ide/macio.o qemu/hw/ide/macio.c: In function 'pmac_ide_atapi_transfer_cb': qemu/hw/ide/macio.c:134:9: error: format '%lx' expects argument of type 'long unsigned int', but argument 3 has type 'hwaddr' [-Werror=format] qemu/hw/ide/macio.c: In function 'pmac_ide_transfer_cb': qemu/hw/ide/macio.c:215:5: error: format '%ld' expects argument of type 'long int', but argument 5 has type 'int64_t' [-Werror=format] qemu/hw/ide/macio.c:222:9: error: format '%lx' expects argument of type 'long unsigned int', but argument 3 has type 'hwaddr' [-Werror=format] qemu/hw/ide/macio.c:264:9: error: format '%lx' expects argument of type 'long unsigned int', but argument 3 has type 'hwaddr' [-Werror=format] cc1: all warnings being treated as errors make: *** [hw/ide/macio.o] Error 1 Signed-off-by: Stefan Weil <sw@weilnetz.de> Acked-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-07-27watchdog: Remove break after exitStefan Weil1-1/+0
This was dead code. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-07-27hw/9pfs: Fix potential memory leak and avoid reuse of freed memoryStefan Weil1-0/+2
The leak was reported by cppcheck. Function proxy_init also calls g_free for ctx->fs_root. Avoid reuse of this memory by setting ctx->fs_root to NULL. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: M. Mohan Kumar <mohan@in.ibm.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-07-26sun4m: add display width and height to the firmware configurationMark Cave-Ayland1-0/+4
Currently the graphics resolution for TCX is fixed at 1024x768, however other framebuffers are capable of supporting additional resolutions. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> CC: Anthony Liguori <aliguori@us.ibm.com> CC: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-26Merge remote-tracking branch 'jliu/or32' into stagingAnthony Liguori1-3/+3
# By Jia Liu # Via Jia Liu * jliu/or32: target-openrisc: Free typename in openrisc_cpu_class_by_name hw/openrisc: Use stderr output instead of qemu_log hw/openrisc: Indent typo Message-id: 1374576458-22808-1-git-send-email-proljc@gmail.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-25pc-testdev: add I/O port to test memory.c auto split/combinePaolo Bonzini1-0/+15
The ports at 0xe8..0xeb have impl.min/max_access_size == 1, so that memory accesses are split and combined by the memory core. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374501278-31549-29-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-25sparc64: unbreakPaolo Bonzini1-19/+28
... by making apb a subclass of TYPE_PCI_HOST_BRIDGE. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374501278-31549-21-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-25sh4: unbreak r2dPaolo Bonzini1-14/+25
... by making sh_pci a subclass of TYPE_PCI_HOST_BRIDGE. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374501278-31549-20-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-25mips: degrade BIOS error to warningPaolo Bonzini4-8/+4
No free MIPS BIOS is available, so it makes little sense to quit. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374501278-31549-19-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-25pc-testdev: remove useless cpu_to_le64/le64_to_cpuPaolo Bonzini1-2/+0
So far the device was only used on little-endian machines. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374501278-31549-18-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-25pc-testdev: support 8 and 16-bit accesses to 0xe0Paolo Bonzini1-2/+9
This will let us use the testdev to test endianness. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374501278-31549-17-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-25isa_mmio: deletePaolo Bonzini2-82/+0
It is not used anymore. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374501278-31549-15-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-25ebus: do not use isa_mmioPaolo Bonzini1-2/+4
This is untested, because ebus does not have a libqos module. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374501278-31549-14-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-25sparc64: remove indirection for I/O port accessPaolo Bonzini1-52/+2
This fixes endianness bugs in I/O port access. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374501278-31549-13-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-25mips_fulong2e: do not use isa_mmioPaolo Bonzini1-15/+10
This board is little-endian, but still isa_mmio should die. :) Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374501278-31549-12-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-25mipssim: do not use isa_mmioPaolo Bonzini1-1/+4
Untested, this board does not support PCI so it cannot run endianness-test. It should fix endianness bugs in I/O port access. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374501278-31549-11-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-25ppc440_bamboo: do not use isa_mmioPaolo Bonzini1-1/+4
This fixes endianness bugs in I/O port access. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374501278-31549-10-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-25mips_malta: do not use isa_mmioPaolo Bonzini1-1/+2
This fixes endianness bugs in I/O port access. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374501278-31549-9-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-25mips_r4k: do not use isa_mmioPaolo Bonzini1-1/+5
This fixes endianness bugs in I/O port access. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374501278-31549-8-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-25mips_jazz: do not use isa_mmioPaolo Bonzini1-1/+4
This fixes endianness bugs in I/O port access. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374501278-31549-7-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-25prep: fix I/O port endiannessPaolo Bonzini1-1/+1
Do not swap endianness here, it will happen during cpu_{in,out}{b,w,l}. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374501278-31549-6-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-25spapr_pci: remove indirection for I/O port accessAlexey Kardashevskiy1-39/+2
This fixes endianness bugs in I/O port access. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374501278-31549-5-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-25ppc_newworld: do not use isa_mmioPaolo Bonzini1-1/+4
This fixes endianness bugs in I/O port access. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374501278-31549-4-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-25ppc_oldworld: do not use isa_mmioPaolo Bonzini1-1/+4
This fixes endianness bugs in I/O port access. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374501278-31549-3-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
generated by cgit v1.2.1 (git 2.18.0) at 2024-07-07 07:34:07 +0000